MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 563

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MPC8533EVTARJ

Manufacturer Part Number
MPC8533EVTARJ
Description
MPU POWERQUICC 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MPC8533EVTARJ

Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
1.067GHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-

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12.4.7.7
The KEU interrupt control register controls the result of detected errors. For a given error (as defined in
Section 12.4.7.6, “KEU Interrupt Status Register
set, then the error is ignored; no error interrupt occurs and the KEU interrupt status register is not updated
Freescale Semiconductor
Bits
51
52
53
54
55
56
57
58
59
60
61
62
63
Signal
OFU
ERE
KSE
DSE
OFE
IFO
IFE
CE
DE
AE
IE
KEU Interrupt Control Register (KEUICR)
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Internal error. an internal processing error was detected while the KEU was processing.
0 No error detected
1 Internal error
Note: This bit will be asserted any time an enabled error condition occurs and can only be cleared by setting
0 No error detected
1 Early read error
was modified while the KEU was processing
0 No error detected
1 Context error
0 No error detected
1 Key size error
0 No error detected
1 Data size error
Data error. Invalid data was written to a register or a reserved mode bit was set.
0 Valid data
1 Reserved or invalid mode selected
Address error. An illegal read or write address was detected within the KEU address space.
0 No error detected
1 Address error
Output FIFO error. The KEU output FIFO was non-empty upon write of KEU data size register.
0 No error detected
1 Output FIFO non-empty error
Input FIFO error. The KEU input FIFO was non-empty upon generation of done interrupt.
0 No error detected
1 Input FIFO non-empty error
Reserved
Input FIFO overflow. The KEU input FIFO has been pushed while full.
0 No error detected
1 Input FIFO has overflowed
Output FIFO underflow. The KEU output FIFO was read while empty.
0 No error detected
1 Output FIFO has underflow error
Reserved
Early read error. A KEU context or IV register was read while the KEU was processing.
Context error. A KEU key register, the key size register, the data size register, the mode register, or IV register
Key size error. An inappropriate value (not 16 or 32) was written to the KEU key size register
Data size error. A value was written to the KEU data size register that is greater than 64 bits.
Table 12-47. KEU Interrupt Status Register Field Descriptions (continued)
the corresponding bit in the interrupt control register or by resetting the KEU.
(KEUISR)”), if the corresponding bit in this register is
Description
Security Engine (SEC) 2.1
12-85

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