MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 42

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

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19.4.1.25
19.5
19.5.1
19.5.1.1
19.5.1.2
19.5.1.3
19.5.1.4
19.5.1.5
19.5.1.5.1
19.5.1.5.2
19.5.1.5.3
19.5.1.6
19.5.1.7
19.5.1.8
19.5.1.8.1
19.5.1.8.2
19.5.1.9
19.5.1.10
19.5.1.11
19.5.2
19.5.3
20.1
20.1.1
20.1.2
20.2
20.3
20.3.1
20.3.2
20.3.2.1
20.3.2.2
20.3.3
20.3.3.1
20.4
20.4.1
20.4.2
20.4.3
20.4.4
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MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Introduction.................................................................................................................... 20-1
Signal Descriptions ........................................................................................................ 20-3
Memory Map and Register Definition........................................................................... 20-3
Functional Description................................................................................................. 20-11
Functional Description................................................................................................ 19-25
Power Management ................................................................................................. 19-25
General-Purpose I/O Signals ................................................................................... 19-33
Interrupt and Local Bus Signal Multiplexing .......................................................... 19-33
Overview.................................................................................................................... 20-2
Features...................................................................................................................... 20-3
Register Summary...................................................................................................... 20-3
Control Registers ....................................................................................................... 20-5
Counter Registers..................................................................................................... 20-10
Performance Monitor Interrupt................................................................................ 20-11
Event Counting ........................................................................................................ 20-12
Threshold Events ..................................................................................................... 20-12
Chaining................................................................................................................... 20-13
SerDes 2 Control Register 1 (SRDS2CR1) ......................................................... 19-25
Relationship Between Core and Device Power Management States................... 19-26
CKSTP_IN is Not Power Management ............................................................... 19-27
Dynamic Power Management.............................................................................. 19-27
Shutting Down Unused Blocks............................................................................ 19-27
Software-Controlled Power-Down States............................................................ 19-27
Power Management Control Fields ..................................................................... 19-28
Power-Down Sequence Coordination.................................................................. 19-29
Interrupts and Power Management ...................................................................... 19-31
Snooping in Power-Down Modes........................................................................ 19-32
Software Considerations for Power Management ............................................... 19-32
Requirements for Reaching and Recovering from Sleep State............................ 19-32
Performance Monitor Global Control Register (PMGC0) .................................... 20-5
Performance Monitor Local Control Registers (PMLCAn, PMLCBn)................. 20-6
Performance Monitor Counters (PMC0–PMC9)................................................. 20-10
Doze Mode ...................................................................................................... 19-28
Nap Mode ........................................................................................................ 19-28
Sleep Mode ...................................................................................................... 19-28
Interrupts and Power Management Controlled by MSR[WE] ........................ 19-31
Interrupts and Power Management Controlled by POWMGTCSR................. 19-31
Device Performance Monitor
Contents
Chapter 20
Title
Freescale Semiconductor
Number
Page