MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 242

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Core Register Summary
6.10.2
6-26
Reset
Reset
58–62
32–33
34–39
SPR 1009
Bits
Bits
56
57
63
W
W
R
R
PLL_MODE
PLL_MODE Read-only for integrated devices.
EN_MAS7_
32
48
PLL_CFG
UPDATE
NOPTI
Name
Name
DCFA
—
—
Hardware Implementation-Dependent Register 1 (HID1)
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
33
49
Figure 6-33. Hardware Implementation-Dependent Register 1 (HID1)
Enable MAS7 update (e500v2 only). Enables updating MAS7 by tlbre and tlbsx.
0 MAS7 is not updated by a tlbre or tlbsx.
1 MAS7 is updated by a tlbre or tlbsx.
Data cache flush assist (e500v2 only). Force data cache to ignore invalid sets on miss replacement
selection.
0 The data cache flush assist facility is disabled
1 The miss replacement algorithm ignores invalid entries and follows the replacement sequence
Reserved, should be cleared.
No-op the data and instruction cache touch instructions.
0 dcbt, dcbtst, and icbt are enabled. On the e500, if CT = 0, icbt is always a no-op, regardless of the
1 dcbt, dcbtst, and icbt are treated as no-ops; dcblc and dcbtls are not.
01 Fixed value for MPC8533E
Reflected directly from configuration input pins (read-only). PLL_CFG[0–4] corresponds to the integer
divide ratio and PLL_CFG5 is the half-mode bit. The following values are supported:
0001_00 Ratio of 2:1
0001_01 Ratio of 5:2 (2.5:1)
0001_10 Ratio of 3:1
0001_11 Ratio of 7:2 (3.5:1)
Note that this value is also reflected to PORPLLSR[e500_Ratio]. See
Status Register (PORPLLSR).”
ASTME ABE
defined by the PLRU bits. This reduces the series of uniquely addressed load or dcbz instructions to
eight per set. The bit should be set just before beginning a cache flush routine and should be cleared
when the series of instructions is complete.
value of NOPTI. If CT = 1, icbt does a touch load to an L2 cache, if one is present.
34
50
Table 6-18. HID0 Field Descriptions (continued)
51
Table 6-19. HID1 Field Descriptions
PLL_CFG
52
All zeros
All zeros
39
Description
Description
40
—
—
Section 19.4.1.1, “POR PLL
Access: Supervisor read/write
Freescale Semiconductor
45
RFXE
46
—
47
63