MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 212

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Core Complex Overview
Two of the data buses are general-purpose data-in buses for reads, and the third is a data-out bus for writes.
The two data-in buses feature support for out-of-order read transactions from two different sources
simultaneously, and all three data buses may be operated concurrently. The address-in bus supports
snooping for external management of the L1 caches and TLBs by other bus masters. The core complex
broadcasts and snoops the cache and TLB management instructions accordingly. It is envisioned that a
wide range of system implementations can be constructed from the defined interface.
5.12
The e500 core provides a performance monitoring capability that allows counting of events such as
processor clocks, instruction cache misses, data cache misses, mispredicted branches, and others. The
count of these events may be configured to trigger a performance monitor exception following the e500
interrupt model. This interrupt is assigned to vector offset register IVOR35.
The register set associated with the performance monitoring function consists of counter registers, a global
control register, and local control registers. These registers are read/write from supervisor mode, and each
register is reflected to a corresponding read-only register for user mode. Two instructions, mtpmr and
mfpmr, are provided for moving data to and from these registers. An overview of the performance
monitoring registers is provided in the following sections.
5.12.1
The PMGC0 register provides global control of the performance monitoring facility from supervisor
mode. From this register all counters may be frozen, unfrozen, or configured to freeze on an enabled
condition or event. Additionally, the performance monitoring facility may be disabled or enabled from this
register. The contents of PMGC0 are reflected to UPMGC0, which may be read from user mode using the
mfpmr instruction.
5.12.2
There are four counter registers (PCM0–PCM3) provided in the performance monitoring facility. These
32-bit registers hold the current count for software-selectable events and can be programmed to generate
an exception on overflow. These registers may be written or read from supervisor mode using the mtpmr
and mfpmr instructions. The contents of these registers are reflected to UPCM0–UPCM3, which can be
read from user mode with mfpmr.
Performance monitor exceptions occur only if all of the following conditions are met:
5-28
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A counter is in the overflow state.
The counter's overflow signaling is enabled.
Overflow exception generation is enabled in PMGC0.
MSR[EE] is set.
Performance Monitoring
Global Control Register
Performance Monitor Counter Registers
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Freescale Semiconductor