MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 175

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

4.4.3.9
DDR1 requires a different voltage level from DDR2.
SDRAM type.
4.4.3.10
The eTSEC width input, shown in
Ethernet controller interface. Note that the value latched on this signal during POR is accessible through
the memory-mapped PORDEVSR (POR device status register) described in
Device Status Register (PORDEVSR).”
This input does not affect the width of the FIFO interface which is always an 8-bit FIFO interface.
4.4.3.11
The eTSEC3 width input, shown in
Ethernet controller interface 3. Note that the value latched on this signal during POR is accessible through
the memory-mapped PORDEVSR (POR device status register) described in
Device Status Register (PORDEVSR).”
The value of this configuration setting does not affect the width of the FIFO interface on eTSEC3, which
is always 8 bits.
Freescale Semiconductor
TSEC1_TX_ER
LGPL0, LGPL1
Functional
Default (1)
Default (11)
Functional
Signal
Signal
DDR SDRAM Type
eTSEC1 Width
eTSEC3 Width
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Reset Configuration
cfg_tsec1_reduce
Reset Configuration
cfg_dram_type[0:1]
Name
Name
Table 4-18. eTSEC1/eTSEC2 Width Configuration
Table
(Binary)
Table
Value
Table 4-17. DDR DRAM Type
0
1
(Binary)
Value
4-18, selects standard versus reduced width for three-speed
00
01
10
11
4-19, selects standard versus reduced width for three-speed
eTSEC1 interface operates in reduced pin mode, either RTBI, RGMII,
RMII, or in 8-bit FIFO mode.
eTSEC1 interface operates in standard width TBI, GMII, MII, or in 8-bit
FIFO mode.
(default)
DDR1
2.5V, CKE low at reset
Reserved
DDR2
1.8V, CKE low at reset (default)
Reserved
Table 4-17
describes the configuration of the DDR
Meaning
Meaning
Section 19.4.1.4, “POR
Section 19.4.1.4, “POR
Reset, Clocking, and Initialization
4-17