MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 791

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

15.5.3.3.9
The MRBLR register is written by the user. It informs the eTSEC how much space is in the receive buffer
pointed to by the RxBD.
15.5.3.3.10 Receive Data Buffer Pointer High Register (RBDBPH)
The RBDBPH register is written by the user with the most significant address bits common to all RxBD
buffer addresses, RxBD[Data Buffer Pointer]. As a consequence, Rx buffers must be placed in a 4 Gbyte
segment of memory whose base address is prefixed by the bits in RBDBPH. The RxBD ring itself can
Freescale Semiconductor
1
1100 0–31
1101 0–31
1110 0–15
1111 0–15
PID
16–25
26–31
0–15
\\
Bits
PID is the property identifier field of the filer table control entry (see RQFCR[PID]) at the same index.
Offset eTSEC1:0x2_4340; eTSEC3:0x2_6340
Reset
1
16–31
16–31
W
R
Bit
Name
MRBL Maximum receive buffer length. MRBL is the number of bytes that the eTSEC receiver writes to the receive
0
—
—
Name
DPT
SPT
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
DIA
SIA
—
—
Maximum Receive Buffer Length Register (MRBLR)
Reserved
buffer. The MRBL register is written by the user with a multiple of 64 for all modes. The eTSEC can write fewer
bytes to the buffer than the value set in MRBL if a condition such as an error or end-of-frame occurs, but it
never exceeds the MRBL value; therefore, user-supplied buffers must be at least as large as the MRBL. MRBL
must be set, together with the number of buffer descriptors, to ensure adequate space for received frames.
See
To ensure that MRBL is a multiple of 64, these bits are reserved and should be cleared.
Section 15.5.3.5.5, “Maximum Frame Length Register
Destination IP address. If an IPv4 header was found, this is the entire destination address. If an IPv6
header was found, this is the 32 most significant bits of the 128-bit destination address. This value
defaults to 0x0000_0000 if no IP header appeared.
Source IP address. If an IPv4 header was found, this is the entire source address. If an IPv6 header was
found, this is the 32 most significant bits of the 128-bit source address. This value defaults to
0x0000_0000 if no IP header appeared.
Reserved, should be written with zero.
Destination port number for TCP or UDP headers. This value defaults to 0x0000 if no TCP or UDP
headers were recognized.
Reserved, should be written with zero.
Source port number for TCP or UDP headers. This value defaults to 0x0000 if no TCP or UDP headers
were recognized.
Figure 15-31
Table 15-33. RQFPR Field Descriptions (continued)
—
Figure 15-31. MRBLR Register Definition
Table 15-34. MRBLR Field Descriptions
describes the definition for the MRBLR.
All zeros
15 16
Description
Description
(MAXFRM),” for further discussion.
MRBL
Enhanced Three-Speed Ethernet Controllers
25 26
Access: Read/Write
—
15-61
31