MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 522

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Security Engine (SEC) 2.1
12.4.3.4
The AFEU context/data size register, shown in
block. This value controls how much data will be processed from the last block. The last message block
must be a multiple of 8, from 8 to 64. If a data size that is not a multiple of 8 bits is written, a data size
error is generated. A data size of 0 is illegal and results in the associated crypto-channel locking, requiring
a crypto-channel and AFEU reset. Only bits 61–63 are checked to determine if there is a data size error.
Since all upper bits are ignored, the entire message length (in bits) can be written to this register.
The context/data size register is also used to specify the context size, when context is used. The context
size is fixed at 2072 bits (259 bytes). When loading context through the FIFO, all context data must be
written prior to writing the context data size. The message data size must be written separately.
Writing to this register signals the AFEU to start processing data from the input FIFO as soon as it is
available. If the value of data size is modified during processing, a context error is generated.
This register is cleared when the AFEU is reset or re-initialized.
12.4.3.5
This register, as shown in
3 self-clearing bits. Note that the AFEU executes an internal reset sequence for hardware reset,
12-44
Address AFEU 0x3_8010
Reset
W
R
0
AFEU Context/Data Size Register (AFEUDSR)
AFEU Reset Control Register (AFEURCR)
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
The device driver will create properly formatted descriptors for situations
requiring a key permute prior to ciphering. When operating the SEC as a
slave (typically for debug), the user must set the AFEU mode register to
perform a permute with key function, then write the key data to AFEU key
registers, then write the key size to the key size register. The AFEU starts
permuting the memory with the contents of the key registers immediately
after the key size is written.
In slave mode, when reloading an existing context, the user must write the
context to the input FIFO, then write the context size (always 2072 bits).
The write of the context size indicates to the AFEU that all context has been
loaded. The user then writes the message data size to the context/data size
register. After this write, the user may begin writing message data to the
FIFO.
Figure
Figure 12-23. AFEU Context/Data Size Register
12-24, allows 3 levels of reset that effect the AFEU only, as defined by
—
Figure
NOTE
NOTE
All zeros
12-23, stores the number of bits in the final message
47
48
Freescale Semiconductor
Access: Read/Write
Data Size
63