MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 1189

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

These register fields and their functional relationship are shown in
Reference Manual has details on accessing these power management control bits.
An external master can also initiate power management requests by setting the DOZ or SLP bits in the
memory-mapped power management control and status register (POWMGTCSR). Because the core
responds to snoops while dozing but not while napping, maintaining cache coherency requires significant
preparation by the core before entering nap mode. For this reason only the core can initiate a nap during
normal operation while other masters can initiate a doze.
19.5.1.7
To preserve cache coherency and otherwise avoid loss of system state, the core’s transition to low-power
modes is coordinated by a set of handshaking signals, shown in
MPC8533E functional blocks that respond to power-down requests. The mode-transition protocol is
executes automatically under these conditions and is shown in
The column in
to the external masters that can write to the POWMGTCSR that resides in the global utilities block. For
the MPC8533E, these are the PCI interfaces. However, note that the core can also write to POWMGTCSR
and, in this case, can initiate power management through the global utilities block.
As shown in
core_stop, or core_tben inputs from the MPC8533E’s power management logic. These inputs may be
prompted by the core (by setting the NAP, DOZE, or SLEEP bits in the HID0 when enabled by setting
MSR[WE]) or by an external master (by setting POWMGTCSR[DOZ,SLP].
Figure 19-27
When enabled, (HID0[TBEN] = 1), the clock source is either the CCB clock divided by eight (the default)
or a synchronized version of the RTC input. For more details, see
Implementation-Dependent Register 0 (HID0).”
Freescale Semiconductor
Low-Power Mode
•
•
Sleep
Doze
Nap
HID0[NAP]—Signals the MPC8533E to initiate nap mode.
HID0[SLEEP]—Signals the MPC8533E to initiate sleep mode.
Figure
Power-Down Sequence Coordination
shows how all the clocking to the core timer facilities is disabled by clearing HID0[TBEN].
Table 19-30. Power Management Entry Protocol and Initiating Functional Units
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Table 19-30
1. Assert core_halt input to core.
2. Wait for core_halted handshake from core.
1. Follow doze protocol
2. Assert core_stop input to core.
3. Wait for core_stopped handshake from core.
1. Follow doze protocol; send stop requests to rest of device.
2. Follow nap protocol.
3. Wait for all interfaces to acknowledge stop requests.
4. Assert ASLEEP, negate READY, power down all clocks except to PIC unit.
19-27, the e500 core enters low-power modes only in response to the core_halt,
showing the global utilities block as initiating a low-power mode corresponds
Entry Protocol
Figure 19-26
Figure
Figure
Section 6.10.1, “Hardware
19-27, and protocols with all other
19-27. The PowerPC e500 Core
and described in
Initiating Functional Unit
Global Utilities
—
√
√
Table
Global Utilities
19-30.
Core
19-29
√
√
√