MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 785

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

15.5.3.3.5
The RBIFX register provides a set of four 6-bit offsets for locating up to four octets in a received frame
and passing them to the receive queue filer as the user-defined ARB property. Through RBIFX a custom
ARB filer property can be constructed from arbitrary bytes, which allows frame filing on the basis of
bitfields not ordinarily provided to the filer, such as bits from the Ethernet preamble or TCP flags. The
value of property ARB is the concatenation of {B0, B1, B2, B3} to 32-bits, where B0–B3 are the bytes as
defined by RBIFX.
Figure 15-26
receive frame via the FIFO packet interface, a value of BnCTL = 01 is not supported unless
RCTRL[PRSFM]=1. In addition, the byte extraction level cannot exceed the parser depth: a value of
BnCTL=10 requires RCTRL[PRSDEP]=1x and a value of BnCTL=11 requires RCTRL[PRSDEP]=11.
For values of BnCTL=10 or BCTL=11, the controller will extract the defined bytes even if it does not
recognize the L3 or L4 header, respectively.
Table 15-30
Freescale Semiconductor
Offset eTSEC1:0x2_4330; eTSEC3:0x2_6330
Reset
\
Bits
Bits
0–1
2–7
30
31
W
R
B0CTL
0
Name
B0OFFSET Offset relative to the header defined by B0CTL that locates byte 0 of property ARB. An effective offset
EN6
EN7
1
B0CTL
Name
describes the RBIFX register.
describes the definition for the RBIFX register. Note: when the eTSEC is configured to
2
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Receive Bit Field Extract Control Register (RBIFX)
Receive queue 6 enable.
0 RxBD ring is not queried for reception. In effect the receive queue is disabled.
1 RxBD ring is queried for reception.
Receive queue 7 enable.
0 RxBD ring is not queried for reception. In effect the receive queue is disabled.
1 RxBD ring is queried for reception.
B0OFFSET
Location of byte 0 of property ARB.
00 Byte 0 is not extracted, and appears as zero in property ARB.
01 Byte 0 is located in the received frame at offset (B0OFFSET – 8) bytes from the first byte of the
10 Byte 0 is located in the received frame at offset B0OFFSET bytes from the byte after the last byte of
11 Byte 0 is located in the received frame at offset B0OFFSET bytes from the byte after the last byte of
of zero points to the first byte of the specified header.
Ethernet DA. A negative effective offset points to bytes of the standard Ethernet preamble.
the layer 2 header.
the layer 3 header.
Table 15-29. RQUEUE Field Descriptions (continued)
7
B1CTL
8
Figure 15-26. RBIFX Register Definition
Table 15-30. RBIFX Field Descriptions
9
10
B1OFFSET
All zeros
15 16
Description
B2CTL
Description
17 18
B2OFFSET
Enhanced Three-Speed Ethernet Controllers
23 24
B3CTL
25 26
Access: Read/Write
B3OFFSET
15-55
31