MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 225

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

6.4
This section describes registers that support branch and CR operations.
6.4.1
Freescale Semiconductor
Reset
CR n Bits
35–56
57–63
CR0[0]
CR0[1]
CR0[2]
Bits
32
33
34
W
R
32
Name
CR0
No. of
bytes
Registers for Branch Operations
SO
OV
CA
CR Bits
—
Condition Register (CR)
32
33
34
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
35 36
Summary overflow. Set when an instruction (except mtspr) sets the overflow bit. Once set, SO remains set
until it is cleared by mtspr[XER] or mcrxr. SO is not altered by compare instructions or by other instructions
(except mtspr[XER] and mcrxr) that cannot overflow. Executing mtspr[XER], supplying the values 0 for
SO and 1 for OV, causes SO to be cleared and OV to be set.
Overflow. X-form add, subtract from, and negate instructions having OE = 1 set OV if the carry out of bit 32
is not equal to the carry out of bit 33, and clear OV otherwise to indicate a signed overflow. X-form multiply
low word and divide word instructions having OE = 1 set OV if the result cannot be represented in 32 bits
(mullwo, divwo, and divwuo) and clear OV otherwise. OV is not altered by compare instructions or by
other instructions (except mtspr[XER] and mcrxr) that cannot overflow.
Carry. Add carrying, subtract from carrying, add extended, and subtract from extended instructions set CA
if there is a carry out of bit 32 and clear it otherwise. CA can be used to indicate unsigned overflow for add
and subtract operations that set CA. Shift right algebraic word instructions set CA if any 1 bits are shifted
out of a negative operand and clear CA otherwise. Compare instructions and instructions that cannot carry
(except Shift Right Algebraic Word, mtspr[XER], and mcrxr) do not affect CA.
Reserved, should be cleared.
Supports emulation of load and store string instructions. Specifies the number of bytes to be transferred by
a load string indexed or store string indexed instruction.
00000
00001
00010
CR1
BI
39 40
Negative (LT)—Set when the result is negative.
For SPE vector compare and vector test instructions:
Set if the high-order element of rA is equal to the high-order element of rB; cleared otherwise.
Positive (GT)—Set when the result is positive (and not zero).
For SPE vector compare and vector test instructions:
Set if the low-order element of rA is equal to the low-order element of rB; cleared otherwise.
Zero (EQ)—Set when the result is zero. For SPE vector compare and vector test instructions:
Set to the OR of the result of the compare of the high and low elements.
Table 6-4. BI Operand Settings for CR Fields
CR2
Figure 6-3. Condition Register (CR)
Table 6-3. XER Field Description
43 44
CR3
All zeros
47 48
Description
CR4
Description
51 52
CR5
55 56
CR6
Access: User read/write
Core Register Summary
59 60
CR7
6-9
63