MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 183
MPC8533EVTARJ
Manufacturer Part Number
MPC8533EVTARJ
Description
MPU POWERQUICC 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8533VTALF.pdf
(112 pages)
2.MPC8533VTALF.pdf
(2 pages)
3.MPC8533VTALF.pdf
(16 pages)
4.MPC8533VTALF.pdf
(1332 pages)
Specifications of MPC8533EVTARJ
Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
1.067GHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
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- MPC8533VTALF PDF datasheet
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Part II
e500 Core Complex and L2 Cache
This part describes the many features of the MPC8533E core processor at an overview level and the
interaction between the core complex and the L2 cache. The following chapters are included:
The e500 processor core is a low-power implementation of the family of reduced instruction set computing
(RISC) embedded processors that implement the Power ISA definition. This part provides additional
information about the architecture as it relates specifically to the e500 core complex and specific details
on how its registers are accessed.
The e500 core complex interacts with the L2 cache through the core complex bus (CCB).
Freescale Semiconductor
•
•
•
Chapter 5, “Core Complex Overview,”
L1 caches and MMU that, together with the core, comprise the core complex.
Chapter 6, “Core Register Summary,”
Chapter 7, “L2 Look-Aside Cache/SRAM,”
the L2 cache can also be addressed directly as memory-mapped SRAM.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
provides a listing of the e500v2 registers in reference form.
provides an overview of the e500v2 core processor and the
describes the L2 cache of the MPC8533E. Note that
II-1
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