MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 1312

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

E–E
E
e500 coherency module (ECM)
e500 core
Index-4
interrupts
memory map/register definition, 13-4
modes of operation, 13-2
overview, 1-17, 13-1
PC16450 UART compatibility, 13-1
performance monitor events, 20-27
register descriptions, 13-4, 13-6–13-19
serial interface data format, 13-2
serial interface operation, 13-20–13-21
signals summary, 13-3
block diagram, 8-1
CCB arbiter, 8-9
CCB interface, 8-10
configuration
error handling
features, 8-2
functional description, 8-9
global data multiplexor, 8-10
I/O arbiter, 8-9
initialization/application information, 8-10–8-11
interrupts
memory map/register definition, 8-3
overview, 1-14, 8-2
performance monitor events, 20-19
register descriptions, 8-3
transaction queue, 8-10
boot mode (POR), 4-15
branch operations
interrupt control logic, 13-23
interrupt enable and control registers, 13-9–13-11
DMA mode selection, 13-23
FIFO mode, 13-22
local loopback mode, 13-22
by acronym, see Register Index
UART0 register offsets, 13-4
UART1 register offsets, 13-4
data transfer, 13-21
START bit, 13-20
STOP bit, 13-21
transaction protocol example, 13-20
see also Signals, DUART
CCB address configuration register (EEBACR), 8-3
CCB port configuration register (EEBPCR), 8-4
error handling registers, 8-6–8-9
ECM error enable register (EEER), 8-7
by acronym, see Register Index
registers, 6-9–6-11
interrupts, 13-23
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
branch target buffer (BTB)
computational operations
debug registers, 6-39–6-45
hardware implementation-dependent registers (HID0–1),
interrupts
L1 caches
memory management unit (MMU)
overview, 1-8
performance monitor
processor control registers, 6-11–6-14
registers
registers, 6-23–6-25
registers, 6-8–6-9
registers, 6-17–6-22
sources, 10-3
registers, 6-28–6-32
registers, 6-32–6-39
registers, 6-48–6-52
BBEAR (branch buffer address register), 6-23
BBTAR (branch buffer target address register), 6-23
BUCSR (branch unit control and status register), 6-24
CR (condition register), 6-9
CSRR0–1 (critical save/restore registers 0–1), 6-17
CTR (count register), 6-11
DACn (data address compare registers 1–2), 6-45
DBCRn (debug control register 0–2), 6-39–6-43
DBSR (debug status register), 6-43
DEAR (data exception address register 0), 6-18
DEC (decrementer register), 6-16
DECAR (decrementer auto-reload register), 6-17
ESR (exception syndrome register), 6-19
GPRs (general-purpose registers), 6-8
HID0–1 (hardware implementation-dependent registers
IACn (instruction address compare registers 1–2), 6-45
IVORn (interrupt vector offset registers), 6-18
IVPR (interrupt vector prefix register), 6-18
L1CFG0–1 (L1 cache configuration registers 0–1), 6-30
L1CSR0–1 (L1 cache status and control registers 0–1),
LR (link register), 6-11
MAS0–MAS6 (MMU assist registers 0–6), 6-35–6-39
MCAR (machine check address register), 6-21
MCSR (machine check syndrome register), 6-21
MCSRR0–1 (machine check save/restore registers 0–1),
MMUCFG (MMU configuration register), 6-32
6-25–6-28
MMU assist registers (MAS0–MAS4, MAS6),
MMU assist registers (MAS0–MAS4,
0–1), 6-25
6-28
6-20
6-35–6-38
MAS6–MAS7), 6-35–6-39
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Index