MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 636

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Local Bus Controller
14-18
Bits
2–3
5–7
8–9
4
UWPL LUPWAIT polarity active low. Sets the polarity of the LUPWAIT signal when in UPM mode.
Name
AM
OP
DS
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Command opcode. Determines the command executed by the UPM n when a memory access hits a UPM
assigned bank. See
00 Normal operation
01 Write to UPM array. On the next memory access that hits a UPM assigned bank, write the contents of the
10 Read from UPM array. On the next memory access that hits a UPM assigned bank, read the contents of
11 Run pattern. On the next memory access that hits a UPM assigned bank, run the pattern written in the
0 LUPWAIT is active high.
1 LUPWAIT is active low.
Address multiplex size. Determines how the address of the current memory cycle can be output on the
address signals. This field is needed when interfacing with devices requiring row and column addresses
multiplexed on the same signals.
Disable timer period. Guarantees a minimum time between accesses to the same memory bank controlled by
UPM n . The disable timer is turned on by the TODT bit in the RAM array word, and when expired, the UPM n
allows the machine access to handle a memory pattern to the same bank. Accesses to a different bank by
the same UPM n is also allowed. To avoid conflicts between successive accesses to different banks, the
minimum pattern in the RAM array for a request serviced, should not be shorter than the period established
by DS.
00 1-bus clock cycle disable period
01 2-bus clock cycle disable period
10 3-bus clock cycle disable period
11 4-bus clock cycle disable period
MDR into the RAM location pointed to by MAD. After the access, MAD is automatically incremented.
the RAM location pointed to by MAD into the MDR. After the access, MAD is automatically incremented.
RAM array. The pattern run starts at the location pointed to by MAD and continues until the LAST bit is set
in the RAM word.
Value LA0–LA15
000
001
010
011
100
101
110
111
Table 14-10. M x MR Field Descriptions (continued)
Section 14.4.4.2, “Programming the UPMs,”
0
0
0
0
0
0
LA16
A8
A7
A6
A5
A4
A3
LA17
A9
A8
A7
A6
A5
A4
Description
LA18
A10
A9
A8
A7
A6
A5
Reserved
Reserved
LA19–LA28 LA29
A11–A20
A10–A19
A9–A18
A8–A17
A7–A16
A6–A15
for important programming considerations.
A21
A20
A19
A18
A17
A16
LA30
A22
A21
A20
A19
A18
A17
Freescale Semiconductor
LA31
A23
A22
A21
A20
A19
A18