MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 1043

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

17.4.2.13 PCI Error Functions
PCI provides for parity and other system errors to be detected and reported. The PCI command register
provides for selective enabling of specific PCI error detection. The PCI bus status register provides PCI
error reporting. This section describes generation and detection of parity and error reporting for the PCI
bus.
17.4.2.13.1 PCI Parity
Generating parity is not optional; it must be performed by all PCI-compliant devices. All PCI transactions,
regardless of type, calculate even parity; that is, the number of ones on the PCI_AD[31:0], PCI_C/BE[3:0],
and PCI_PAR signals all sum to an even number.
Parity provides a way to determine, on each transaction, if the initiator successfully addressed the target
and transferred valid data. The PCI_C/BE[3:0] signals are included in the parity calculation to ensure that
the correct bus command is performed (during the address phase) and correct data is transferred (during
the data phase). The agent responsible for driving the bus must also drive even parity on the PAR and
PCI_PAR64 signal one clock cycle after a valid address phase or valid data transfer, as shown in
Figure
During the address and data phases, parity covers all 32 address/data signals and 4 command/byte enable
signals, regardless of whether all lines carry meaningful information. Byte lanes not actually transferring
data must contain stable (albeit meaningless) data and are included in parity calculation. During
configuration, special-cycle, or interrupt-acknowledge commands; some address lines are not defined, but
are driven to stable values and are included in parity calculation.
Freescale Semiconductor
PCI_PAR, PCI_PAR64
17-60.
PCI_C/BE[7:0]
PCI_DEVSEL
PCI_AD[63:0]
PCI_FRAME
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
PCI_PERR
PCI_SERR
PCI_TRDY
PCI_IRDY
SYSCLK
ADDR
CMD
Figure 17-60. PCI Parity Operation
Byte Enables
DATA
ADDR
CMD
Byte Enables
DATA
PCI Bus Interface
17-65