MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 1107
MPC8533EVTARJ
Manufacturer Part Number
MPC8533EVTARJ
Description
MPU POWERQUICC 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8533VTALF.pdf
(112 pages)
2.MPC8533VTALF.pdf
(2 pages)
3.MPC8533VTALF.pdf
(16 pages)
4.MPC8533VTALF.pdf
(1332 pages)
Specifications of MPC8533EVTARJ
Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
1.067GHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
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18.3.8.3.5
The secondary latency timer register does not apply to PCI Express. It must be read-only and return all
zeros when read.
18.3.8.3.6
Note that this device does not support inbound I/O transactions. The I/O base register is shown in
Figure
Table 18-58
18.3.8.3.7
Note that this device does not support inbound I/O transactions. The I/O limit register is shown in
Figure
Freescale Semiconductor
Offset 0x1C
Offset 0x1D
Reset
Reset
18-62.
18-62.
W
W
R
R
Bits
7–4
3–0
describes the I/O base register fields.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
PCI Express Secondary Latency Timer Register—0x1B
PCI Express I/O Base Register—0x1C
PCI Express I/O Limit Register—0x1D
7
7
Address Decode Type Specifies the number of I/O address bits.
I/O Start Address
Table 18-59. PCI Express I/O Base Register Field Description
Name
I/O Start Address
I/O Limit Address
Figure 18-63. PCI Express I/O Base Register
Figure 18-64. PCI Express I/O Limit Register
Specifies bits 15:12 of the I/O space start address
0x00 16-bit I/O address decode
0x01 32-bit I/O address decode
All other settings reserved.
4
4
All zeros
All zeros
3
3
Description
Address Decode Type
Address Decode Type
PCI Express Interface Controller
Access: Read-only
Access: Read-only
0
0
18-59
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