MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 231

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

6.6.2
Freescale Semiconductor
Reset
32–33
34–35
38–39
43–46
47–50
51–63
SPR 336
Bits
36
37
40
41
42
W w1c
R ENW
1
32
Set by hardware. Read with mfspr and cleared with mtspr by writing ones to any TSR bit positions to be cleared and
zeros in all other bit positions.
WPEXT Watchdog timer period extension (see the description for WP)
FPEXT Fixed-interval timer period extension (see the description for FP)
Name
WRC
ARE
WIE
DIE
WP
FIE
FP
—
—
WIS
w1c
Timer Status Register (TSR)
33
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Watchdog timer period. When concatenated with WPEXT, specifies one of 64-bit locations of the time base
used to signal a watchdog timer exception on a transition from 0 to 1.
WPEXT[0–3] || WP[0–1] = 0b00_0000 selects TBU[32] (the msb of the TB)
WPEXT[0–3] || WP[0–1] = 0b11_1111 selects TBL[63] (the lsb of the TB)
may be set by software but cannot be cleared by software, except by a software-induced reset. Once written
to a non-zero value, WRC may no longer be altered by software.
00 No watchdog timer reset can occur.
01 Force processor checkstop on second timeout of watchdog timer
10 Assert processor reset output ( core_hreset_req ) on second timeout of watchdog timer
11 Reserved
Watchdog timer interrupt enable
0 Watchdog timer interrupts disabled
1 Watchdog timer interrupts enabled
0 Decrementer interrupts disabled
1 Decrementer interrupts enabled
Fixed interval timer period. When concatenated with FPEXT, FP specifies one of 64 bit locations of the time
base used to signal a fixed-interval timer exception on a transition from 0 to 1.
FPEXT[0–3] || FP[0–1] = 0b00_0000 selects TBU[32] (the msb of the TB)
FPEXT[0–3] || FP[0–1] = 0b11_1111 selects TBL[63] (the lsb of the TB)
Fixed interval interrupt enable
0 Fixed interval interrupts disabled
1 Fixed interval interrupts enabled
reaches 0000_0001. See EREF: A Reference for Freescale Book E and the e500 Core .
0 Auto-reload disabled
1 Auto-reload enabled
Reserved, should be cleared.
Reserved, should be cleared.
Watchdog timer reset control. This value is written into TSR[WRS] when a watchdog event occurs. WRC
Decrementer interrupt enable
Auto-reload enable. Controls whether the DECAR value is reloaded into the DEC when the DEC value
34
WRS
w1c
35
w1c
DIS
36
Figure 6-11. Timer Status Register (TSR)
w1c
FIS
Table 6-9. TCR Field Descriptions
37
38
All zeros
Description
—
Access: Supervisor w1c
Core Register Summary
6-15
63
1