MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 103
MPC8533EVTARJ
Manufacturer Part Number
MPC8533EVTARJ
Description
MPU POWERQUICC 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8533VTALF.pdf
(112 pages)
2.MPC8533VTALF.pdf
(2 pages)
3.MPC8533VTALF.pdf
(16 pages)
4.MPC8533VTALF.pdf
(1332 pages)
Specifications of MPC8533EVTARJ
Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
1.067GHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Available stocks
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Manufacturer
Quantity
Price
Company:
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Manufacturer:
Freescale Semiconductor
Quantity:
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MPC8533EVTARJA
Manufacturer:
FREESCAL
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Company:
Part Number:
MPC8533EVTARJA
Manufacturer:
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Quantity:
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- MPC8533VTALF PDF datasheet
- MPC8533VTALF PDF datasheet #2
- MPC8533VTALF PDF datasheet #3
- MPC8533VTALF PDF datasheet #4
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- Download datasheet (18Mb)
Freescale Semiconductor
•
•
•
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— AFEU—ARC four execution unit
— MDEU—message digest execution unit
— KEU—Kasumi execution unit
— RNG—random number generator
— XOR engine accelerates parity checking in RAID storage applications.
Dual I
— Two-wire interface
— Multiple master support
— Master or slave I
— On-chip digital filtering rejects spikes on the bus
Boot sequencer
— Optionally loads configuration data from serial ROM at reset via the I
— Can be used to initialize configuration registers and/or memory
— Supports extended I
— Data integrity checked with preamble signature and CRC
DUART
— Two 4-wire interfaces (SIN, SOUT, RTS, CTS)
— Programming model compatible with the original 16450 UART and the PC16550D
Local bus controller (LBC)
— Multiplexed 32-bit address and data bus operating at up to 166 MHz
— Eight chip selects support eight external slaves.
— Up to eight-beat burst transfers
— The 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller.
— Three protocol engines available on a per chip select basis:
— Parity support
— Default boot ROM chip select with configurable bus width (8, 16, or 32 bits)
– Implements a stream cipher compatible with the RC4 algorithm
– 40- to 128-bit programmable key
– SHA with 160- or 256-bit message digest
– MD5 with 128-bit message digest
– HMAC with either algorithm
– Implements F8 algorithm for encryption and F9 algorithm for integrity checking
– Also supports A5/3 and GEA-3 algorithms
– General-purpose chip select machine (GPCM)
– Three user programmable machines (UPMs)
– Dedicated single data rate SDRAM controller
2
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
C controllers
2
C mode support
2
C addressing mode
2
C1 interface
Overview
1-5
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