MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 1030
MPC8533EVTARJ
Manufacturer Part Number
MPC8533EVTARJ
Description
MPU POWERQUICC 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8533VTALF.pdf
(112 pages)
2.MPC8533VTALF.pdf
(2 pages)
3.MPC8533VTALF.pdf
(16 pages)
4.MPC8533VTALF.pdf
(1332 pages)
Specifications of MPC8533EVTARJ
Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
1.067GHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
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PCI Bus Interface
Figure 17-51
Figure 17-52
17.4.2.8
A PCI transaction may be terminated by either the initiator or the target. The initiator is ultimately
responsible for concluding all transactions, regardless of the cause of the termination. All transactions are
concluded when PCI_FRAME and PCI_IRDY are both negated, indicating the bus is idle.
17.4.2.8.1
Normally, a master initiates termination by negating PCI_FRAME and asserting PCI_IRDY. This
indicates to the target that the final data phase is in progress. The final data transfer occurs when both
PCI_TRDY and PCI_IRDY are asserted. The transaction is considered complete when data is transferred
17-52
PCI_DEVSEL
PCI_FRAME
PCI_FRAME
PCI_EVSEL
PCI_TRDY
PCI_TRDY
PCI_C/BE
PCI_IRDY
PCI_C/BE
PCI_IRDY
Transaction Termination
illustrates a PCI single-beat write transaction.
illustrates a PCI burst write transaction.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
SYSCLK
SYSCLK
PCI_AD
PCI_AD
Master-Initiated Termination
Figure 17-51. PCI Single-Beat Write Transaction
ADDR
ADDR
CMD
CMD
Figure 17-52. PCI Burst Write Transaction
Byte Enables 1 Byte Enables 2
DATA1
DATA2
Byte Enables
DATA
Byte Enables 3
DATA3
DATA4
BEs 4
Freescale Semiconductor
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