MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 686

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Local Bus Controller
signal of the corresponding bank depends on the value of each CSTn bit.
control LCSn signals.
14.4.4.4.3
If BRn[MSEL] of the accessed memory bank selects a UPM on the currently requested cycle, the selected
UPM affects the assertion and negation of the appropriate LBS[0:3] signal. The timing of all four
byte-select signals is specified in the RAM word. However, LBS[0:3] are also controlled by the port size
of the accessed bank, the number of bytes to transfer, and the address accessed.
Figure 14-60
The uppermost byte select (LBS0), when asserted, indicates that LAD[0:7] contains valid data during a
cycle. Likewise, LBS1 indicates that LAD[8:15] contains valid data, LBS2 indicates that LAD[16:23]
contains valid data, and LBS3 indicates that LAD[24:31] contains valid data. For a UPM refresh timer
request, all LBS[0:3] signals are asserted/negated by the UPM according to the refresh pattern only.
14-68
shows how UPMs control LBS[0:3].
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Byte Select Signal Timing (BST n )
UPMA/B/C
SDRAM
UPMA
UPMB
UPMC
GPCM
Figure 14-59. LCS n Signal Selection
Figure 14-60. LBS Signal Selection
BR n [MSEL]
MUX
Bank Selected
BR n [MSEL]
Bank Selected
MUX
BR n [PS]
Byte-Select
Byte count
Logic
Switch
A[29:31]
Figure 14-59
LCS0
LCS1
LCS2
LCS3
LCS4
LCS5
LCS6
LCS7
LBS0
LBS1
LBS2
LBS3
Freescale Semiconductor
shows how UPMs