MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 1321

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Index
Freescale Semiconductor
device-specific configuration space registers,
extended configuration space registers, 18-81–18-89
memory-mapped registers, 18-5
memory limit register, 18-61
minimum grant (EP-mode) register, 18-55
prefetchable base upper 32 bits register, 18-63
prefetchable limit upper 32 bits register, 18-63
prefetchable memory base register, 18-62
prefetchable memory limit register, 18-62
primary bus number register, 18-57
revision ID register, 18-47
secondary bus number register, 18-58
secondary status register, 18-60
subordinate bus number register, 18-58
subsystem vendor ID register, 18-53
vendor ID register, 18-44
capabilities register, 18-70
capability ID register, 18-70
data capabilities register, 18-71
device control register, 18-71
device status register, 18-72
link capabilities register, 18-73
link control register, 18-73
link status register, 18-74
MSI message address register, 18-79
MSI message capability ID register, 18-78
MSI message control register, 18-78
MSI message data register, 18-80
MSI message upper address register, 18-79
power management capabilities register, 18-68
power management capability ID register, 18-68
power management data register, 18-69
power management status and control register, 18-69
root control register, 18-77
root status register, 18-78
slot capabilities register, 18-75
slot control register, 18-76
slot status register, 18-76
advanced error capabilities and control register, 18-86
advanced error reporting capability ID register, 18-82
correctable error mask register, 18-85
correctable error source ID register, 18-89
correctable error status register, 18-85
error source ID register, 18-89
header log register, 18-87
root error command register, 18-88
root error status register, 18-88
uncorrectable error mask register, 18-83
uncorrectable error severity register, 18-84
uncorrectable error status register, 18-82
ATMU registers, 18-19–18-29
18-67–18-80
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
PCI Local Bus Specification configuration registers
PCI/PCI-X controller
signals summary, 18-4
see PCI/PCI-X controller, registers
64-bit/32-bit bus, 17-5
address bus decoding, 17-47
address translation and mapping unit (ATMU)
arbiter configuration (POR), 4-20, 17-5
block diagram, 17-2
burst operations
bus arbitration, 17-5, 17-42
bus protocol, 17-45
clocking, 17-45, 17-50
commands
configuration cycles, 17-58
configuration space addressing, 17-48
data bus width (POR), 4-19
debug mode
error handling, 17-65–17-66
features, 17-4
functional description, 17-42
I/O impedance (POR), 4-20
I/O space addressing, 17-48
initialization/application information, 17-67–17-70
interrupts
see also Signals, PCI Express
inbound windows (4), 2-10, 17-19
outbound windows (4), 17-16
cache wrap mode, 17-47
linear incrementing, 17-47
burst operation, 17-45
command encodings, 17-46
command register, 17-31, 17-59
encodings, 17-46
interrupt-acknowledge transactions, 17-63
special-cycle, 17-64
source and target ID (PCI_AD[63:59]), 21-25
address/data parity, 17-54, 17-65, 17-66
detection and reporting, 17-65
reporting
retry transactions, 17-53
target-abort, 17-53
target-disconnect, 17-53
error enable register, 17-26
by acronym, see Register Index
configuration access registers, 18-9–18-12,
error management registers, 18-29–18-42
IP block revision registers, 18-18–18-19
pwr mgmt and message registers, 18-13–18-18
PERR and SERR signals, 17-66
target-initiated termination, 17-53
18-42–18-43
Index-13
P–P