MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 220

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Core Register Summary
The e500 core implements 64-bit GPRs, the upper 32 bits of which are used only with 64-bit load, store,
and merge instructions.
6.2.1
Table 6-1
number indicates whether an SPR is accessible from user- or supervisor-level software. An mtspr or
mfspr instruction that specifies an unsupported SPR number is considered an invalid instruction.
In
6-4
Abbreviation
Table 6-1
CSRR0
CSRR1
•
•
•
•
•
•
•
•
SPR
CTR
Section 6.12, “MMU Registers”
Section 6.13, “Debug Registers”
Section 6.14, “Signal Processing and Embedded Floating-Point Status and Control Register
(SPEFSCR)”
Reserved fields are always ignored for the purposes of determining access type.
R/W, R, and W (read/write, read only, and write only) indicate that all the non-reserved fields in a
register have the same access type.
w1c indicates that all of the non-reserved fields in a register are cleared by writing ones to them.
Mixed indicates a combination of access types.
Special is used when no other category applies. In this case the register figure and field description
table should be read carefully.
Table 6-1. Base and Embedded Category Special-Purpose Registers (by SPR Abbreviation)
summarizes SPRs. The SPR numbers are used in the instruction mnemonics. Bit 5 in an SPR
and in the register figures and field descriptions, the following access definitions apply:
Special-Purpose Registers (SPRs)
Critical save/restore register 0
Critical save/restore register 1
Count register
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Writing to the following registers requires synchronization, as described in
the “Synchronization Requirements” section in the “Register Model”
chapter of the PowerPC™ e500 Core Family Reference Manual.
•
•
•
•
•
•
BTB locking registers—BBEAR, BBTAR, and BUCSR
DBCRn
HIDn
L1CSRn
MMU registers—MASn, MMUCSR0, PIDn
SPEFSCR
Name
Decimal
Defined SPR Number
58
59
9
NOTE
00000 01001
00001 11010
00001 11011
Binary
Read/Write
Read/Write
Read/Write
Access
Supervisor
Only
Freescale Semiconductor
Yes
Yes
No
6.7.1.1/6-17
6.7.1.2/6-17
6.4.3/6-11
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