MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 13

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Paragraph
Number
8.2.1
8.2.1.1
8.2.1.2
8.2.1.3
8.2.1.4
8.2.1.5
8.2.1.6
8.2.1.7
8.2.1.8
8.2.1.9
8.3
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.4
9.1
9.2
9.2.1
9.3
9.3.1
9.3.2
9.3.2.1
9.3.2.2
9.3.2.3
9.4
9.4.1
9.4.1.1
9.4.1.2
9.4.1.3
9.4.1.4
9.4.1.5
9.4.1.6
9.4.1.7
9.4.1.8
9.4.1.9
Freescale Semiconductor
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Functional Description..................................................................................................... 8-9
Initialization/Application Information ........................................................................... 8-10
Introduction...................................................................................................................... 9-1
Features ............................................................................................................................ 9-2
External Signal Descriptions ........................................................................................... 9-3
Memory Map/Register Definition ................................................................................... 9-9
Register Descriptions................................................................................................... 8-3
I/O Arbiter.................................................................................................................... 8-9
CCB Arbiter................................................................................................................. 8-9
Transaction Queue ..................................................................................................... 8-10
Global Data Multiplexor............................................................................................ 8-10
CCB Interface ............................................................................................................ 8-10
Modes of Operation ..................................................................................................... 9-3
Signals Overview......................................................................................................... 9-3
Detailed Signal Descriptions ....................................................................................... 9-5
Register Descriptions................................................................................................. 9-11
ECM CCB Address Configuration Register (EEBACR) ........................................ 8-3
ECM CCB Port Configuration Register (EEBPCR) ............................................... 8-4
ECM IP Block Revision Register 1 (EIPBRR1) ..................................................... 8-5
ECM IP Block Revision Register 2 (EIPBRR2) ..................................................... 8-5
ECM Error Detect Register (EEDR) ....................................................................... 8-6
ECM Error Enable Register (EEER) ....................................................................... 8-7
ECM Error Attributes Capture Register (EEATR) .................................................. 8-7
ECM Error Low Address Capture Register (EELADR) ......................................... 8-8
ECM Error High Address Capture Register (EEHADR) ........................................ 8-9
Memory Interface Signals........................................................................................ 9-5
Clock Interface Signals............................................................................................ 9-9
Debug Signals.......................................................................................................... 9-9
Chip Select Memory Bounds (CSn_BNDS).......................................................... 9-11
Chip Select Configuration (CSn_CONFIG).......................................................... 9-11
DDR SDRAM Timing Configuration 3 (TIMING_CFG_3)................................. 9-13
DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)................................. 9-14
DDR SDRAM Timing Configuration 1 (TIMING_CFG_1)................................. 9-16
DDR SDRAM Timing Configuration 2 (TIMING_CFG_2)................................. 9-18
DDR SDRAM Control Configuration (DDR_SDRAM_CFG)............................. 9-20
DDR SDRAM Control Configuration 2 (DDR_SDRAM_CFG_2)...................... 9-23
DDR SDRAM Mode Configuration (DDR_SDRAM_MODE)............................ 9-25
DDR Memory Controller
Contents
Chapter 9
Title
Number
Page
xiii