MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 1053

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

PCI Express defines the connection between two devices as a link, which can be composed of a single or
multiple lanes. Each lane consists of a differential pair for transmitting (TXn and TXn) and a differential
pair for receiving (RXn and RXn) with an embedded data clock.
Table 18-2
18.3
The PCI Express interface supports the following register types:
18.3.1
The PCI Express memory mapped registers are accessed by reading and writing to an address comprised
of the base address (specified in the CCSRBAR on the local side or the PEXCSRBAR on the PCI Express
Freescale Semiconductor
SD1_RX[7:0]
SD1_RX[7:0]
SD1_TX[7:0]
SD1_TX[7:0]
SD2_RX0
SD2_RX0
SD2_TX0
SD2_TX0
•
•
Signal
Memory-mapped registers—these registers control PCI Express address translation, PCI error
management, and PCI Express configuration register access. These registers are described in
Section 18.3.1, “PCI Express Memory Mapped Registers,”
PCI Express configuration registers contained within the PCI Express configuration space—these
registers are specified by the PCI Express specification for every PCI Express device. These
registers are described in
subsections.
Memory Map/Register Definitions
contains detailed descriptions of the external PCI Express interface signals.
PCI Express Memory Mapped Registers
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
I/O
O
O
I
I
Table 18-2. PCI Express Interface Signals—Detailed Signal Descriptions
Receive data. The receive data signals carry PCI Express packet information. Subject to
“I/O Port
available on SD1_RX[7:4], and PCI Express controller 3 is available on SD2_RX0.
Receive data, inverted. SD1_RX[7:0] and SD2_RX0 are the inverted forms of the receive data signals
(SD1_RX[7:0] and SD2_RX0).
Transmit data. The transmit data signals carry PCI Express packet information. Subject to
“I/O Port
available on SD1_TX[7:4], and PCI Express controller 3 is available on SD2_TX0.
Transmit data, inverted. SD1_TX[7:0] and SD2_TX0 are the inverted form of the transmit data signals
(SD1_TX[7:0] and SD2_TX0).
Meaning
Meaning
Meaning
Meaning
Timing Assertion/Negation—As described in the PCI Express Base Specification, Revision 1.0a .
Timing Assertion/Negation—As described in the PCI Express Base Specification, Revision 1.0a .
Timing Assertion/Negation—As described in the PCI Express Base Specification, Revision 1.0a .
Timing Assertion/Negation—As described in the PCI Express Base Specification, Revision 1.0a .
State
State
State
State
Selection, PCI Express controller 1 is available on SD1_RX[3:0], PCI Express controller 2 is
Selection, PCI Express controller 1 is available on SD1_TX[3:0], PCI Express controller 2 is
Asserted/Negated—Represents data being received from the PCI Express interface.
Asserted/Negated—Represents the inverse of data being received from the PCI Express
interface.
Asserted/Negated—Represents data being transmitted to the PCI Express interface.
Asserted/Negated—Represents the inverse of data being transmitted to the PCI Express
interface.
Section 18.3.7, “PCI Express Configuration Space Access,”
Description
and its subsections.
PCI Express Interface Controller
Section 4.4.3.6,
Section 4.4.3.6,
and its
18-5