MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 784
MPC8533EVTARJ
Manufacturer Part Number
MPC8533EVTARJ
Description
MPU POWERQUICC 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8533VTALF.pdf
(112 pages)
2.MPC8533VTALF.pdf
(2 pages)
3.MPC8533VTALF.pdf
(16 pages)
4.MPC8533VTALF.pdf
(1332 pages)
Specifications of MPC8533EVTARJ
Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
1.067GHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Enhanced Three-Speed Ethernet Controllers
15-54
16–23
Bits
10
11
12
13
14
15
24
25
26
27
28
29
9
Name
EN0
EN1
EN2
EN3
EN4
EN5
EX1
EX2
EX3
EX4
EX5
EX6
EX7
—
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Receive queue 1 extract enable.
0 Data transferred by DMA to this RxBD ring is not extracted to cache.
1 Data transferred by DMA to this RxBD ring undergoes extraction according to ATTR register.
Receive queue 2 extract enable.
0 Data transferred by DMA to this RxBD ring is not extracted to cache.
1 Data transferred by DMA to this RxBD ring undergoes extraction according to ATTR register.
Receive queue 3 extract enable.
0 Data transferred by DMA to this RxBD ring is not extracted to cache.
1 Data transferred by DMA to this RxBD ring undergoes extraction according to ATTR register.
Receive queue 4 extract enable.
0 Data transferred by DMA to this RxBD ring is not extracted to cache.
1 Data transferred by DMA to this RxBD ring undergoes extraction according to ATTR register.
Receive queue 5 extract enable.
0 Data transferred by DMA to this RxBD ring is not extracted to cache.
1 Data transferred by DMA to this RxBD ring undergoes extraction according to ATTR register.
Receive queue 6 extract enable.
0 Data transferred by DMA to this RxBD ring is not extracted to cache.
1 Data transferred by DMA to this RxBD ring undergoes extraction according to ATTR register.
Receive queue 7 extract enable.
0 Data transferred by DMA to this RxBD ring is not extracted to cache.
1 Data transferred by DMA to this RxBD ring undergoes extraction according to ATTR register.
Reserved
Receive queue 0 enable.
0 RxBD ring is not queried for reception. In effect the receive queue is disabled.
1 RxBD ring is queried for reception.
Receive queue 1 enable.
0 RxBD ring is not queried for reception. In effect the receive queue is disabled.
1 RxBD ring is queried for reception.
Receive queue 2 enable.
0 RxBD ring is not queried for reception. In effect the receive queue is disabled.
1 RxBD ring is queried for reception.
Receive queue 3 enable.
0 RxBD ring is not queried for reception. In effect the receive queue is disabled.
1 RxBD ring is queried for reception.
Receive queue 4 enable.
0 RxBD ring is not queried for reception. In effect the receive queue is disabled.
1 RxBD ring is queried for reception.
Receive queue 5 enable.
0 RxBD ring is not queried for reception. In effect the receive queue is disabled.
1 RxBD ring is queried for reception.
Table 15-29. RQUEUE Field Descriptions (continued)
Description
Freescale Semiconductor
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