MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 270

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

L2 Look-Aside Cache/SRAM
7.1.1
The L2 cache has the following characteristics:
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Supports 36-bit address space
Write-through, front-side cache
— Front-side design provides easier cache access for the I/O masters, such as Ethernet
— Write-through design is more efficient on the processor bus for front-side caches
Valid, locked, and stale states (no modified state)
Two input data buses (64 and 128 bits wide) and one output data bus (128 bits wide)
All accesses are fully pipelined and non-blocking (allows hits under misses)
256-Kbyte array organized as 1024 eight-way sets of 32-byte cache lines
Eight-way set associativity with a pseudo-LRU (7-bit) replacement algorithm.
— High level of associativity yields good performance even with many lines locked or used as
I/O devices can store data into the cache in a process called ‘stashing.’
— Stashing is indicated for global I/O writes either by a transaction attribute or by a
— Regions of the cache can be reserved exclusively for stashing to prevent pollution of processor
Processor L2 cache regions are configurable to allocate instructions, data, or both.
— External masters can force data to be allocated into the cache through programmed memory
Data ECC on 64-bit boundaries (single-error correction, double-error detection)
Tag arrays use 21 tag bits and 1 tag parity bit per line.
Multiple cache locking methods supported
— Individual line locks are set and cleared by using e500 cache locking APU instructions—Data
— A lock attribute can be attached to write operations.
— Individual line locks are set and cleared through core-initiated instructions, by external reads
— The entire cache can be locked by setting a configuration register appropriately.
Lock clearing methods
— Individual locks can be cleared by cache-locking APU instructions—Data Cache Block Lock
— Flash clearing of all instruction and/or data locks is done by writes to configuration registers.
— An unlock attribute can be attached to a read instruction.
SRAM regions
programmable memory range
cache regions.
ranges or special transaction types (stashing).
– 1, 2, or 4 ways can be configured for stashing only
Cache Block Touch and Lock Set (dcbtls), Data Cache Block Touch for Store and Lock Set
(dcbtstls), and Instruction Cache Block Touch and Lock Set (icbtls).
or writes, or by accesses to programmed memory ranges defined in L2 cache external write
address registers (L2CEWARn).
Clear (dcblc) and Instruction Cache Block Lock Clear (icblc)—or by a snooped flush unless
entire cache is locked.
L2 Cache and SRAM Features
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Freescale Semiconductor