MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 1310

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

D–D
Coherency rules
Commands
Configuration
Configuration space
Configuration, control, and status
Context ID registers, 21-23–21-24
CR (condition register), see e500 core, registers
Crypto-channels, see Security engine (SEC)
CSRR0–1 (critical save/restore registers 0–1), see e500 core,
CTR (count register), see e500 core, registers
CTS, see DUART_CTS[0:1]
Index-2
I
LBC bus clocks and clock ratios, 14-3
overview, 1-20
PCI/PCI-X clocking, 17-45, 17-50
POR settings
L2 cache, 7-28
PCI, see PCI/PCI-X controller
DDR, 9-11–9-32, 9-43
ECM
eTSEC interfaces, 15-180–15-206
LBC
PCI/PCI-X
PIC
POR, see Power-on-reset (POR)
PCI Express, 18-42
PCI/PCI-X addressing, 17-48
accessing CCSR memory from external masters, 2-10, 2-11
accessing CCSRs, 4-4
alternate configuration space (ALTBAR and ALTCAR),
boot page translation, 4-7
CCSR memory map, 2-10–2-14
CCSRBAR update guidelines, 4-4
memory map/register definition, 4-4
organization of CCSR memory, 2-11
2
C
clock stretching, 11-17
clock synchronization, 11-16
input synchronization and digital filter, 11-16
clock ratio register (LCRR), 14-30
e500 core PLL ratio, 4-12
system/CCB PLL ratio, 4-11
CCB address configuration register (EEBACR), 8-3
CCB port configuration register (EEBPCR), 8-4
configuration register (LBCR), 14-29
SDRAM configurations supported, 14-47
configuration access registers, 17-60
configuration cycles, 17-58
configuration space header, 17-58
global configuration register, 10-19
registers
4-6
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
D
DACn (data address compare registers 1–2), see e500 core,
Data cache
DBCRn (debug control register 0–2), see e500 core, registers
DBSR (debug status register), see e500 core, registers
DDR controller
see L2 cache/SRAM
address signal mappings, 9-4
battery-backed RAM and forced self-refresh mode, 9-72
block diagram, 9-1, 9-41
clock distribution, 9-57
clocks
configuration, example, 9-43
data beat ordering, 9-64
DDR2 calibration, 19-21
debug mode
driver impedance calibration, 9-8
error checking and correcting (ECC), 7-39, 9-65
error handling, 9-34, 9-67
features, 9-2
functional description, 9-41
I/O impedance control, 19-21
initialization/application information, 9-68
interrupts, 9-37
memory map/register definition, 9-9
modes of operation, 9-3
on-die termination for CSs, 9-8
overview, 1-14
page mode and logical bank retention, 9-64
performance monitor events, 20-17
register descriptions, 9-11
SDRAM operation, 9-45
registers
disabling, 19-22
signal selection (POR), 4-20
source and target ID, 21-4, 21-25
testing ECC with error injection, 9-33–9-34
programming different memory types, 9-69
by acronym, see Register Index
configuration registers, 9-11–9-32
error handling registers, 9-34–9-41
error injection registers, 9-33–9-34
address multiplexing, 9-47
initialization sequence, 9-72
JEDEC standard interface commands, 9-52
mode-set command timing, 9-58
organizations supported, 9-45
refresh operation, 9-60
registered DIMM mode, 9-59
timing, 9-54
power-saving modes, 9-61
timing, 9-61
Freescale Semiconductor
Index