MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 634

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Local Bus Controller
14.3.1.2.4
Figure 14-5
machine.
Table 14-8
14-16
17–18
19–21
23–25
27–30
0–16
Bits
22
26
31
Offset 0x004 (OR0)
Reset
W
R
PMSEL Page mode select. Selects page mode for the SDRAM connected to the memory controller bank.
ROWS Number of row address lines. Sets the number of row address lines in the SDRAM device.
Name
COLS Number of column address lines. Sets the number of column address lines in the SDRAM device.
XAM
EAD
0x00C (OR1)
0x014 (OR2)
0x01C (OR3)
AM
0
—
—
describes BRn fields for SDRAM mode.
shows the bit fields for ORn when the corresponding BRn[MSEL] selects the SDRAM
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
SDRAM address mask. Masks corresponding BR n bits. Masking address bits independently allows external
devices of different size address ranges to be used. Address mask bits can be set or cleared in any order in
the field, allowing a resource to reside in more than one area of the address map. AM can be read or written
at any time.
0 Corresponding address bits are masked.
1 The corresponding address bits are used in the comparison with address signals.
Extended address mask. Masks the corresponding BR n [XBA] bits, effectively extending the address mask
(AM) by 2 bits.
000 7
001 8
010 9
011 10
Reserved
000 9
001 10
010 11
011 12
0 Back-to-back page mode (normal operation). Page is closed when the bus becomes idle.
1 Page is kept open until a page miss or refresh occurs.
Reserved
External address latch delay. Allow extra bus clock cycles when using external address latch (LALE).
0 No additional bus clock cycles (LALE asserted for one bus clock cycle only)
1 Extra bus clock cycles are added (LALE is asserted for the number of bus clock cycles specified by
Option Registers (OR n )—SDRAM Mode
LCRR[EADC]).
Figure 14-5. Option Registers (OR n ) in SDRAM Mode
0x024 (OR4)
0x02C (OR5)
0x034 (OR6)
0x03C (OR7)
Table 14-8. OR n
AM
100 11
101 12
110 13
111 14
100 13
101 14
110 15
111 Reserved
—
SDRAM Field Descriptions
All zeros
16 17 18 19
Description
XAM
COLS — ROWS PMSEL
21 22 23
25
26
Freescale Semiconductor
Access: Read/Write
27
—
30
EAD
31