PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 100

• Manufacturer Part Number: PEB2256H-V12
• Description: IC INTERFACE LINE 3.3V 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2256H-V12

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2256H-V12; PEB2256H-V12IN

4.4.7.2
The HDLC controller of channel 1 supports the signaling system #7 (SS7) which is
described in ITU-Q.703. The following description assumes, that the reader is familiar
with the SS7 protocol definition.
SS7 support must be activated by setting the MODE register. Data stored in the transmit
FIFO (XFIFO) is sent automatically. The SS7 protocol is supported by the following
hardware features in transmit direction:
• transmission of flags at the beginning of each Signaling Unit
• bit stuffing (zero insertion)
• calculation of the CRC16 checksum:
Each Signaling Unit written to the transmit FIFO (XFIFO, 2 32 bytes) is sent once or
repeatedly including flags, CRC checksum and stuffed bits. After e.g. an MSU has been
transmitted completely, the FALC56 optionally starts sending of FISUs containing the
forward sequence number (FSN) and the backward sequence number (BSN) of the
previously transmitted Signaling Unit. Setting bit CCR5.AFX causes Fill In Signaling
Units (FISUs) to be sent continuously, if no HDLC or Signaling Unit (SU) is to be
transmitted from XFIFO. During update of XFIFO, automatic transmission is interrupted
and resumed after update is completed. The internally generated FISUs contain FSN
and BSN of the last transmitted Signaling Unit written to XFIFO.
Using CMDR.XREP = 1, the contents of XFIFO can be sent continuously. Clearing of
CMDR.XRES/SRES stops the automatic repetition of transmission. This function is also
available for HDLC frames, so no flag generation, CRC byte generation and bit stuffing
is necessary.
Example: After an MSU has been sent repetitively and XREP has been cleared, FISUs
are sent automatically.
4.4.7.3
The FALC56 supports the S
• the access through register XSW
• the access through registers XSA(8:4), capable of storing the information for a
• the access through the 64 byte deep XFIFO of the signaling controller (HDLC channel
This S
frames where the signaling controller automatically processes the HDLC protocol. Any
combination of S
selected by XC0.SA(8:4).
Data Sheet
The transmitter adds the checksum to each Signaling Unit.
complete multiframe
1 only)
a
-bit access gives the opportunity to transparent a bit stream as well as HDLC
Support of Signaling System #7
S
a
-Bit Access (E1)
a
-bits which shall be inserted in the outgoing data stream can be
a
-bit signaling of time slot 0 of every other frame as follows:
100
Functional Description E1
FALC56 V1.2
PEB 2256
2002-08-27