PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 160
PEB2256H-V12
Manufacturer Part Number
PEB2256H-V12
Description
IC INTERFACE LINE 3.3V 80-MQFP
Manufacturer
Infineon Technologies
Datasheet
1.PEB2256H-V12.pdf
(490 pages)
Specifications of PEB2256H-V12
Applications
*
Interface
*
Voltage - Supply
*
Package / Case
80-SQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEB2256H-V12
PEB2256H-V12IN
PEB2256H-V12IN
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Quantity
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Part Number:
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5.4.6
The transmit line monitor compares the transmit line current on XL1 and XL2 with an on-
chip transmit line current limiter. The monitor detects faults on the primary side of the
transformer indicated by a highly increased transmit line current (more than 120 mA for
at least 3 consecutive pulses sourced by V
by setting the transmit line driver XL1/2 into high-impedance state automatically (if
enabled by XPM2.DAXLT = 0). The current limiter checks the actual current value of
XL1/2 and if the transmit line current drops below the detection limit the high-impedance
state is cleared.
Two conditions are detected by the monitor: transmit line de-jitteredity (more than 31
consecutive zeros) indicated by FRS1.XLO and transmit line high current indicated by
FRS1.XLS. In both cases a transmit line monitor status change interrupt is provided.
Figure 53
5.4.7
Similar to the receive signaling controller the same signaling methods and the same time
slot assignment are provided. The FALC56 performs the following signaling and data link
methods.
5.4.7.1
The transmit signaling controller of the FALC56 performs the flag generation, CRC
generation, zero bit stuffing and programmable idle code generation. Buffering of
transmit data is done in the 64 byte deep XFIFO. The signaling information is internally
multiplexed with the data applied to port XDI or XSIG.
In signaling controller transparent mode, fully transparent data transmission without
1)
Data Sheet
shorts between XL1 or XL2 and V
Transmit Line Monitor (T1/J1)
Transmit Signaling Controller (T1/J1)
HDLC or LAPD access
Transmit Line Monitor Configuration (T1/J1)
DDX
XL1
XL2
are not detected
160
Monitor
Line
DDX
TRI
1)
) and protects the device from damage
Functional Description T1/J1
Shaper
Pulse
XDATA
ITS10936
FALC56 V1.2
PEB 2256
2002-08-27
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