PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 155
PEB2256H-V12
Manufacturer Part Number
PEB2256H-V12
Description
IC INTERFACE LINE 3.3V 80-MQFP
Manufacturer
Infineon Technologies
Datasheet
1.PEB2256H-V12.pdf
(490 pages)
Specifications of PEB2256H-V12
Applications
*
Interface
*
Voltage - Supply
*
Package / Case
80-SQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEB2256H-V12
PEB2256H-V12IN
PEB2256H-V12IN
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PEB2256H-V12
Manufacturer:
Infineon Technologies
Quantity:
10 000
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Similar to the receive line interface three different data types are supported:
Figure 50
Table 39
Parameter
Characteristic Impedance [ ]
R
t2 : t1
1)
• Ternary Signal
• Dual-rail data PCM(+), PCM(-) at multifunction ports XDOP and XDON with 50% or
• Unipolar data on port XOID is transmitted in NRZ (non return to zero) with 100% duty
5.4.3
The transmit jitter attenuator DCO-X circuitry generates a "jitter-free" transmit clock and
meets the following requirements: PUB 62411, PUB 43802, TR-TSY 009,TR-TSY 253,
TR-TSY 499 and ITU-T I.431 and G.703. The DCO-X circuitry works internally with the
Data Sheet
1
This value refers to an ideal transformer without any parasitics. Any transformer resistance or other parasitic
resistances have to be taken into account when calculating the final value of the output serial resistors.
Selection between B8ZS or simple AMI coding with zero code suppression (B7
stuffing) is provided. B7 stuffing can be disabled on a per time slot basis (Clear
Channel capability). Selected by FMR0.XC1/0 and LIM1.DRS = 0.
100% duty cycle and with programmable polarity. Line coding is done in the same way
as in ternary interface mode. Selected by FMR0.XC1 = 1 and LIM1.DRS = 1.
cycle or in CMI code with or without (SIC3.CMI) preprocessed by B8ZS coding to a
fiber-optical interface. Clocking off data is done with the rising edge of the transmit
clock XCLK (1544 kHz) and with a programmable polarity. Selection is done by
FMR0.XC1 = 0 and LIM1.DRS = 1.
( 1%) [ ]
Single-rail data is converted into a ternary signal which is output on pins XL1 and XL2.
Transmit Jitter Attenuator (T1/J1)
Transmitter Configuration (T1/J1)
Recommended Transmitter Configuration Values (T1/J1)
Line
t
1
t
2
155
R
R
1
1
XL1
XL2
100
T1
Functional Description T1/J1
FALC
R
ITS10968
1 : 2.4
2
1)
FALC56 V1.2
110
PEB 2256
J1
2002-08-27
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