PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 143
PEB2256H-V12
Manufacturer Part Number
PEB2256H-V12
Description
IC INTERFACE LINE 3.3V 80-MQFP
Manufacturer
Infineon Technologies
Datasheet
1.PEB2256H-V12.pdf
(490 pages)
Specifications of PEB2256H-V12
Applications
*
Interface
*
Voltage - Supply
*
Package / Case
80-SQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEB2256H-V12
PEB2256H-V12IN
PEB2256H-V12IN
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PEB2256H-V12
Manufacturer:
Infineon Technologies
Quantity:
10 000
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5.2.5
Normally, this kind of multiframe structure only makes sense when using the CAS
robbed-bit signaling. The multiframe alignment signal is located at the FS-bit position of
every other frame (refer to
Table 34
Frame Number
1
2
3
4
5
6
7
8
9
10
11
12
There are two possibilities of remote alarm (yellow alarm) indication:
• Bit 2 = 0 in each time slot of a frame, selected with bit FMR0.SRAF = 0
• The last bit of the multiframe alignment signal (bit 1 of frame 12) changes from "0" to
5.2.5.1
In the synchronous state terminal framing (FT-bits) and multiframing (FS-bits) are
observed, independently. Further reaction on framing errors depends on the selected
synchronization/resynchronization procedure (by bit FMR2.SSP):
• FMR2.SSP = 0: terminal frame and multiframe synchronization are combined.
• FMR2.SSP = 1: terminal frame and multiframe synchronization are separated
Data Sheet
"1", selected with bit FMR0.SRAF = 1.
Two errors within 4/5/6 framing bits (by bits FMR4.SSC1/0) of one of the above leads
to the asynchronous state for terminal framing and multiframing. Additionally to the bit
FRS0.LFA, loss of multiframe alignment is reported by bit FRS0.LMFA.
The resynchronization procedure starts with synchronizing upon the terminal framing.
If the pulse framing has been regained, the search for multiframe alignment is
initiated. Multiframe synchronization has been regained after two consecutive correct
multiframe patterns have been received.
Two errors within 4/5/6 terminal framing bits lead to the same reaction as described
12-Frame Multiframe (D4 or SF Format, T1/J1)
Synchronization Procedure
12-Frame Multiframe Structure (T1/J1)
F
1
–
0
–
1
–
0
–
1
–
0
–
T
Table
34).
143
F
–
0
–
0
–
1
–
1
–
1
–
0
S
Functional Description T1/J1
Signaling Channel
Designation
A
B
FALC56 V1.2
PEB 2256
2002-08-27
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