PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 21

• Manufacturer Part Number: PEB2256H-V12
• Description: IC INTERFACE LINE 3.3V 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2256H-V12

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2256H-V12; PEB2256H-V12IN

• Channel loop back, line loop back or payload loop back capabilities (TR54016)
• Pseudo-random binary sequence generator and monitor
• Clear channel capabilities (T1/J1)
• Loop-timed mode
Signaling Controller
• Three HDLC controllers
• Supports signaling system #7
• CAS/CAS-BR controller with last look capability, enhanced CAS-register access and
• DL-channel protocol for ESF format according to ANSI T1.403 specification or
• DL-bit access for F72 (SLC96) format (T1/J1)
• Generates periodical performance report according to ANSI T1. 403
• Provides access to serial signaling data streams
• Multiframe synchronization and synthesis according to ITU-T G.732
• Alarm insertion and detection (AIS and LOS in time slot 16)
• Transparent mode
• FIFO buffers (64 bytes deep) for efficient transfer of data packets
• Time slot assignment
• Time-slot 0 S
• HDLC access to any S
Microprocessor Interface
• 8/16-bit microprocessor bus interface (Intel or Motorola type)
• All registers directly accessible (byte or word access)
• Multiplexed and non-multiplexed address bus operations
• Hard/software reset options
• Extended interrupt capabilities
• One-second timer (internal or external timing reference)
Data Sheet
(framed or unframed)
Bit stuffing, CRC check and generation, flag generation, flag and address recognition,
handling of bit oriented functions
delimitation, alignment and error detection according to ITU-Q.703
processing of fill in signaling units, processing of errored signaling units
freeze signaling indication
according to AT&T TR54016 (T1/J1)
Any combination of time slots selectable for data transfer independent of signaling
mode (useful for fractional T1/J1 applications)
a
8...4-bit handling via FIFOs (E1)
a
-bit combination (E1)
21
FALC56 V1.2
Introduction
PEB 2256
2002-08-27