PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 94

• Manufacturer Part Number: PEB2256H-V12
• Description: IC INTERFACE LINE 3.3V 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2256H-V12

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2256H-V12; PEB2256H-V12IN

4.4
4.4.1
The serial bit stream is processed by the transmitter which has the following functions:
• Frame/multiframe synthesis of one of the two selectable framing formats
• Insertion of service and data link information
• AIS generation (Alarm indication signal)
• Remote alarm generation
• CRC generation and insertion of CRC bits
• CRC bits inversion in case of a previously received CRC error
• Idle code generation per DS0
The frame/multiframe boundaries of the transmitter can be externally synchronized by
using the SYPX/XMFS pin. Any change of the transmit time slot assignment
subsequently produces a change in the framing bit positions on the line side. This feature
is required if signaling and service bits are routed through the switching network and are
inserted in transmit direction by the system interface.
In loop-timed configuration (LIM2.ELT = 1) disconnecting the control of the transmit
system highway from the transmitter is done by setting XSW.XTM. The transmitter is
now in a free running mode without any possibility to update the multiframe position in
case of changing the transmit time slot assignment. The framing bits are generated
independently of the transmit system interface. For proper operation the transmit elastic
buffer size should be programmed to 2 frames.
The contents of selectable time slots can be overwritten by the pattern defined by
register IDLE. The selection of “idle channels” is done by programming the four-byte
registers ICB1…ICB4.
Data Sheet
Transmit Path in E1 Mode
Transmitter (E1)
94
Functional Description E1
FALC56 V1.2
PEB 2256
2002-08-27