PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 115

• Manufacturer Part Number: PEB2256H-V12
• Description: IC INTERFACE LINE 3.3V 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2256H-V12

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2256H-V12; PEB2256H-V12IN

4.6.3
To perform an effective circuit test a payload loop is implemented. The payload loop-
back (FMR2.PLB) loops the data stream from the receiver section back to transmitter
section. The looped data passes the complete receiver including the wander and jitter
compensation in the receive elastic store and is output on pin RDO. Instead of the data
an AIS signal (FMR2.SAIS) can be sent to the system interface.
The framing bits, CRC4 and spare bits are not looped, if XSP.TT0 = 0. They are
generated by the FALC56 transmitter. If the PLB is enabled the transmitter and the data
on pins XL1/2 or XDOP/XDON are clocked with SCLKR instead of SCLKX. If
XSP.TT0 = 1 the received time slot 0 is sent back transparently to the line interface. Data
on the following pins is ignored: XDI, XSIG, SCLKX, SYPX and XMFS. All the received
data is processed normally.
Figure 38
Data Sheet
RL1
RL2
XL1
XL2
Payload Loop-Back
Payload Loop (E1)
Clock +
Data
Recovery
Trans.
Framer
RCLK
Rec.
Framer
115
Elast.
Store
Elast.
Store
Functional Description E1
AIS-GEN
MUX
FALC56 V1.2
PEB 2256
ITS09748
2002-08-27
RDO
SCLKR
XDI
SCLKX