PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 366
![no-image](/images/manufacturer_photos/0/3/327/infineon_technologies_sml.jpg)
PEB2256H-V12
Manufacturer Part Number
PEB2256H-V12
Description
IC INTERFACE LINE 3.3V 80-MQFP
Manufacturer
Infineon Technologies
Datasheet
1.PEB2256H-V12.pdf
(490 pages)
Specifications of PEB2256H-V12
Applications
*
Interface
*
Voltage - Supply
*
Package / Case
80-SQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEB2256H-V12
PEB2256H-V12IN
PEB2256H-V12IN
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PEB2256H-V12
Manufacturer:
Infineon Technologies
Quantity:
10 000
- Current page: 366 of 490
- Download datasheet (6Mb)
Line Interface Mode 1 (Read/Write)
Value after reset: 00
LIM1
CLOS
RIL(2:0)
DCOC
Data Sheet
CLOS
7
Clear data in case of LOS
0 =
1 =
Receive Input Threshold
Only valid if analog line interface is selected (LIM1.DRS = 0).
“No signal” is declared if the voltage between pins RL1 and RL2 drops
below the limits programmed by bits RIL(2:0) and the received data
stream has no transition for a period defined in the PCD register.
The threshold where “no signal” is declared is programmable by the
RIL(2:0) bits depending on bit LIM0.EQON.
Note: LIM1.RIL(2:0) must be programmed before LIM0.EQON = 1 is
set.
See the DC characteristics for detail.
DCO-R Control
0 =
1 =
Note: If IPC.SSYF = 1, external reference clock frequency is 8.0 kHz
RIL2
H
independent of DCOC.
Normal receiver mode, receive data stream is transferred
normally in long-haul mode
In long-haul mode received data is cleared (driven low), as
soon as LOS is detected
1.544 MHz reference clock for the DCO-R circuitry provided on
pin SYNC.
2.048 MHz reference clock for the DCO-R circuitry provided on
pin SYNC.
RIL1
RIL0
366
DCOC
JATT
RL
T1/J1 Registers
FALC56 V1.2
DRS
0
PEB 2256
2002-08-27
(37)
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