PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 252

• Manufacturer Part Number: PEB2256H-V12
• Description: IC INTERFACE LINE 3.3V 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2256H-V12

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2256H-V12; PEB2256H-V12IN

LDC(1:0)
LAC(1:0)
FLLB
LLBP
Data Sheet
Length Deactivate (Down) Code
These bits defines the length of the LLB deactivate code which is
programmable in register LCR2.
00 = Length: 5 bit
01 = Length: 6 bit, 2 bit, 3 bit
10 = Length: 7 bit
11 = Length: 8 bit, 2 bit, 4bit
Length Activate (Up) Code
These bits defines the length of the LLB activate code which is
programmable in register LCR3.
00 = Length: 5 bit
01 = Length: 6 bit, 2 bit, 3 bit
10 = Length: 7 bit
11 = Length: 8 bit, 2 bit, 4 bit
Framed Line Loop-Back/Invert PRBS
Depending on bit LCR1.XPRBS this bit enables different functions:
LCR1.XPRBS = 0:
0 =
1 =
Invert PRBS
LCR1.XPRBS = 1:
0 =
1 =
Line Loop-Back Pattern
LCR1.XPRBS = 0
0 =
1 =
LCR1.XPRBS = 1 or LCR1.EPRM = 1
0 =
1 =
The line loop-back code is transmitted including framing bits.
LLB code overwrites the FS/DL-bits.
The line loop-back code is transmitted unframed. LLB code
does not overwrite the FS/DL-bits.
The generated PRBS is transmitted not inverted.
The PRBS is transmitted inverted.
Fixed line loop-back code according to ANSI T1. 403.
Enable user-programmable line loop-back code by register
LCR2/3.
2
2
15
20
-1
-1
252
FALC56 V1.2
E1 Registers
PEB 2256
2002-08-27