PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 73

• Manufacturer Part Number: PEB2256H-V12
• Description: IC INTERFACE LINE 3.3V 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2256H-V12

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2256H-V12; PEB2256H-V12IN

4.1.14
The signaling controller can be programmed to operate in various signaling modes. The
FALC56 performs the following signaling and data link methods.
4.1.14.1 HDLC or LAPD access
The FALC56 offers three independent HDLC channels. All of them provide the following
features:
• 64 byte receive FIFO for each channel
• 64 byte transmit FIFO for each channel
• transmission in one of 31 time slots
• transmission in even frames only, odd frames only or both
• bit positions to be used in selected time slots are maskable
• HDLC or transparent mode
• flag detection
• CRC checking
• bit-stuffing
• flexible address recognition (1 byte, 2 bytes)
• C/R-bit processing (according to LAPD protocol)
In addition to this, HDLC channel 1 provides:
• SS7 support
• BOM (bit oriented message) support
• use of time slot 0 (up to 32 time slots)
• use of S
• flexibility to insert and extract data during certain time slots, any combination of time
In case of common channel signaling the signaling procedure HDLC/SDLC or LAPD
according to Q.921 is supported. The signaling controller of the FALC56 performs the
flag detection, CRC checking, address comparison and zero-bit removing. The received
data flow and the address recognition features can be performed in very flexible way, to
satisfy almost any practical requirements. Depending on the selected address mode, the
FALC56 performs a 1 or 2-byte address recognition. If a 2-byte address field is selected,
the high address byte is compared with the fixed value FEH or FCH (group address) as
well as with two individually programmable values in RAH1 and RAH2 registers.
According to the ISDN LAPD protocol, bit 1 of the high byte address is interpreted as
command/response bit (C/R) and is excluded from the address comparison. Buffering of
receive data is done in a 64 byte deep RFIFO.
Data Sheet
(time slot number programmable for each channel individually)
(programmable for each channel individually)
(any bit position can be enabled for each channel individually)
slots can be programmed independently for the receive and transmit direction
a
Receive Signaling Controller (E1)
-bits
73
Functional Description E1
FALC56 V1.2
PEB 2256
2002-08-27