PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 392
PEB2256H-V12
Manufacturer Part Number
PEB2256H-V12
Description
IC INTERFACE LINE 3.3V 80-MQFP
Manufacturer
Infineon Technologies
Datasheet
1.PEB2256H-V12.pdf
(490 pages)
Specifications of PEB2256H-V12
Applications
*
Interface
*
Voltage - Supply
*
Package / Case
80-SQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEB2256H-V12
PEB2256H-V12IN
PEB2256H-V12IN
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PEB2256H-V12
Manufacturer:
Infineon Technologies
Quantity:
10 000
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RCRC2
XCRC2
ITF2
XMFA2
RFT12, RFT02
Data Sheet
Receive CRC ON/OFF - HDLC Channel 2
Only applicable in non-auto mode.
If this bit is set, the received CRC checksum is written to RFIFO2
(CRC-ITU-T: 2 bytes). The checksum, consisting of the 2 last bytes in
the received frame, is followed in the RFIFO2 by the status
information byte (contents of register RSIS2). The received CRC
checksum will additionally be checked for correctness. If non-auto
mode is selected, the limits for “valid frame” check are modified.
Transmit CRC ON/OFF - HDLC Channel 2
If this bit is set, the CRC checksum will not be generated internally. It
has to be written as the last two bytes in the transmit FIFO (XFIFO2).
The transmitted frame is closed automatically with a closing flag.
Interframe Time Fill - HDLC Channel 2
Determines the idle (= no data to be sent) state of the transmit data
coming from the signaling controller.
0
1
Transmit Multiframe Aligned - HDLC Channel 2
Determines the synchronization between the framer and the
corresponding signaling controller.
0 =
1 =
RFIFO2 Threshold Level - HDLC Channel 2
The size of the accessible part of RFIFO2 can be determined by
programming these bits. The number of valid bytes after an RPF
interrupt is given in the following table:
RFT12
0
0
1
1
The value of RFT(1:0)2 can be changed dynamically if reception is
not running or after the current data block has been read, but before
the command CMDR3.RMC2 is issued (interrupt controlled data
transfer).
Continuous logical "1" is output
Continuous flag sequences are output ("01111110" bit patterns)
The contents of the XFIFO2 is transmitted without multiframe
alignment.
The contents of the XFIFO2 is transmitted multiframe aligned.
RFT02
0
1
0
1
Size of Accessible Part of RFIFO2
32 bytes (default value)
16 bytes
4 bytes
2 bytes
392
T1/J1 Registers
FALC56 V1.2
PEB 2256
2002-08-27
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