PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 335

• Manufacturer Part Number: PEB2256H-V12
• Description: IC INTERFACE LINE 3.3V 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2256H-V12

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2256H-V12; PEB2256H-V12IN

XRES
XHF
XTF
XME
SRES
Data Sheet
Note: During cyclic transmission the XREP-bit has to be set with every
Transmitter Reset
The transmit framer and transmit line interface excluding the system
clock generator and the pulse shaper are reset. However the contents
of the control registers is not deleted.
Transmit HDLC Frame - HDLC Channel 1
After having written up to 32 bytes to the XFIFO, this command
initiates the transmission of a HDLC frame.
Transmit Transparent Frame - HDLC Channel 1
Initiates the transmission of a transparent frame without HDLC
framing.
Transmit Message End - HDLC Channel 1
Indicates that the data block written last to the transmit FIFO
completes the current frame. The FALC56 can terminate the
transmission operation properly by appending the CRC and the
closing flag sequence to the data.
Signaling Transmitter Reset - HDLC Channel 1
The transmitter of the signaling controller is reset. XFIFO is cleared of
any data and an abort sequence (seven 1s) followed by interframe
time fill is transmitted. In response to XRES an XPR interrupt is
generated.
This command can be used by the CPU to abort a frame currently in
transmission.
Note: The maximum time between writing to the CMDR register and
Note: If SCLKX is used to clock the transmission path, commands to
write operation to CMDR.
the execution of the command takes 2.5 periods of the current
system data rate. Therefore, if the CPU operates with a very
high clock rate in comparison with the FALC56's clock, it is
recommended that bit SIS.CEC should be checked before
writing to the CMDR register to avoid any loss of commands.
the HDLC transmitter should only be sent while this clock is
available. If SCLKX is missing, the command register is
blocked after an HDLC command is given.
335
T1/J1 Registers
FALC56 V1.2
PEB 2256
2002-08-27