PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 37

• Manufacturer Part Number: PEB2256H-V12
• Description: IC INTERFACE LINE 3.3V 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2256H-V12

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2256H-V12; PEB2256H-V12IN

Table 3
Pin
No.
77
78
Data Sheet
Pin
No.
C3
B3
Pin Definitions - Clock Generation (cont’d)
Symbol
CLK2
SEC
FSC
Input (I)
Output (O)
Supply (S)
O + PU
I + PU
O
O
Function
System Clock of DCO-X
Output of the de-jittered system clock
generated by the DCO-X circuit. Frequency
selection is done by setting control bits in PC5/
6.
E1: 16.384 MHz, 8.192 MHz, 4.096 MHz or
2.048 MHz
T1/J1: 12.352 MHz, 6.176 MHz, 3.088 MHz or
1.544 MHz
After reset this output is inactive and internally
pulled high.
Note: If DCO-X is not used, no clock is output
One-Second Timer Input
A pulse with logical high level for at least two
2.048-MHz cycles triggers the internal one-
second timer. After reset this pin is configured
to be an input. If not connected, an internal
pullup transistor ensures high input level (see
register GPC1).
One-Second Timer Output
Activated high every second for two 2.048-
MHz clock cycles.
Optionally an 8-kHz frame synchronization
pulse is output via this pin. The
synchronization pulse is active high or low for
one 2.048/1.544-MHz cycle (pulse width = 488
ns for E1and 648 ns or T1/J1).
37
on pin CLK2 (SIC1.XBS(1:0) = 00 and
CMR1.DXJA = 1; buffer bypass and no
jitter attenuation)
Pin Descriptions
FALC56 V1.2
PEB 2256
2002-08-27