PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 139

• Manufacturer Part Number: PEB2256H-V12
• Description: IC INTERFACE LINE 3.3V 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2256H-V12

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2256H-V12; PEB2256H-V12IN

5.2
5.2.1
Activated with bit FMR1.PMOD = 1.
PCM line bit rate
Single frame length
Framing frequency
Organization
Selection of one of the four permissible framing formats is performed by bits FMR4.FM1/
0. These formats are:
F4
F12
ESF
F72
The operating mode of the FALC56 is selected by programming the carrier data rate and
characteristics, line code, multiframe structure, and signaling scheme.
The FALC56 implements all of the standard and/or common framing structures PCM24
(T1/J1, 1.544 Mbit/s) carriers. The internal HDLC controller supports all signaling
procedures including signaling frame synchronization/synthesis in all framing formats.
After reset, the FALC56 must be programmed with FMR1.PMOD = 1 to enable the T1/
J1 (PCM24) mode. Switching between the framing formats is done by bit FMR4.FM1 0
for the receiver and for the transmitter.
5.2.2
Synchronization status is reported by bit FRS0.LFA (Loss Of Frame Alignment). Framing
errors (pulse frame and multiframe) are counted by the Framing Error Counter FEC.
Asynchronous state is reached if
2 out of 4 (bit FMR4.SSC1/0 = 00), or
2 out of 5 (bit FMR4.SSC1/0 = 01), or
2 out of 6 (bit FMR4.SSC1/0 = 10), or
4 consecutive multiframe pattern in ESF format are incorrect (bit FMR4.SSC1/0 = 11).
If auto mode is enabled, counting of framing errors is interrupted.
The resynchronization procedure is controlled by either one of the following procedures:
• Automatically (FMR4.AUTO = 1). Additionally, it can be triggered by the user by
Data Sheet
setting/resetting one of the bits FMR0.FRS (force resynchronization) or FMR0.EXLS
(external loss of frame).
:
:
:
:
Framer Operating Modes (T1/J1)
General
General Aspects of Synchronization
4-frame multiframe
12-frame multiframe (D4)
Extended Superframe (F24)
72-frame multiframe (SLC96)
:
:
:
:
1.544 Mbit/s
193 bit, No. 1…193
8 kHz
24 time slots, No. 1…24
with 8 bits each, No. 1…8 and one preceding F-bit
139
Functional Description T1/J1
FALC56 V1.2
PEB 2256
2002-08-27