PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 427

• Manufacturer Part Number: PEB2256H-V12
• Description: IC INTERFACE LINE 3.3V 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2256H-V12

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2256H-V12; PEB2256H-V12IN

LA
Receive Byte Count Low - HDLC Channel 1 (Read)
RBCL
Together with RBCH, bits RBC(11:8), indicates the length of a received frame (1 to 4095
bytes). Bits RBC(4:0) indicate the number of valid bytes currently in RFIFO. These
registers must be read by the CPU following a RME interrupt.
Received Byte Count High - HDLC Channel 1 (Read)
Value after reset: 000
RBCH
OV
RBC(11:8)
Data Sheet
RBC7
7
7
Low Byte Address Compare - HDLC Channel 1
Significant in HDLC modes only.
The low byte address of a 2-byte address field, or the single address
byte of a 1-byte address field is compared to two registers. (RAL1,
RAL2).
0
1
Note: Not valid in SS7 mode. Bit LA has to be ignored, if SS7 mode is
Counter Overflow - HDLC Channel 1
More than 4095 bytes received.
Receive Byte Count - HDLC Channel 1 (most significant bits)
Together with RBCL (bits RBC7 0) indicates the length of the
received frame.
xxxxx
RAL2 has been recognized
RAL1 has been recognized
selected.
OV
427
RBC11
RBC10
RBC9
T1/J1 Registers
RBC0
RBC8
FALC56 V1.2
0
0
PEB 2256
2002-08-27
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(67)