PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 211

• Manufacturer Part Number: PEB2256H-V12
• Description: IC INTERFACE LINE 3.3V 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2256H-V12

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2256H-V12; PEB2256H-V12IN

8.3.8
The FALC56 supports the DL-channel protocol using the ESF or F72 (SLC96) format as
follows (HDLC channel 1 only):
• Sampling of DL-bits is done on a multiframe basis and stored in the registers
• If enabled via CCR1.EDLX/EITS = 10, the DL-bit information is stored in the receive
Data Sheet
RDL(3:1). A receive multiframe begin interrupt is provided to read the received data
DL-bits. The contents of registers XDL(3:1) is subsequently sent out on the transmit
multiframe basis if it is enabled via FMR1.EDL. A transmit multiframe begin interrupt
requests for writing new information to the DL-bit registers.
FIFO of the signaling controller. The DL-bits stored in the XFIFO are inserted into the
outgoing data stream. If CCR1.EDLX is cleared, a HDLC frame or a transparent frame
can be sent or received via the RFIFO/XFIFO.
Data Link Access in ESF/F72 Format (T1/J1)
211
Signaling Controller Operating Modes
FALC56 V1.2
PEB 2256
2002-08-27