PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 346
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PEB2256H-V12
Manufacturer Part Number
PEB2256H-V12
Description
IC INTERFACE LINE 3.3V 80-MQFP
Manufacturer
Infineon Technologies
Datasheet
1.PEB2256H-V12.pdf
(490 pages)
Specifications of PEB2256H-V12
Applications
*
Interface
*
Voltage - Supply
*
Package / Case
80-SQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEB2256H-V12
PEB2256H-V12IN
PEB2256H-V12IN
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PEB2256H-V12
Manufacturer:
Infineon Technologies
Quantity:
10 000
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FRS
SRAF
EXLS
SIM
Data Sheet
00 = NRZ (optical interface)
01 = CMI (1T2B+B8ZS), (optical interface)
10 = AMI coding with Zero Code Suppression (ZCS, B7-stuffing),
11 = B8ZS Code (ternary or digital dual-rail interface)
A transition from low to high forces the frame aligner to execute a
resynchronization of the pulse frame. In the asynchronous state, a
new frame position is assumed at the next candidate if there is one.
Otherwise, a new frame search with the meaning of a general reset is
started. In the synchronous state this bit has the same meaning as bit
FMR0.EXLS except if FMR2.MCSP = 1.
0 =
1 =
External Loss Of Frame
With a low to high transition a new frame search is started. This has
the meaning of a general reset of the internal frame alignment unit.
Synchronous state is reached only if there is one definite framing
candidate. In the case of multiple candidates, the setting of the bit
FMR0.FRS forces the receiver to lock onto the next available framing
position.
Alarm Simulation
Setting/resetting this bit initiates internal error simulation of: AIS (blue
alarm), loss-of-signal (red alarm), loss of frame alignment, remote
(yellow) alarm, slip, framing errors, CRC errors, code violations. The
error counters FEC, CVC, CEC, EBC are incremented.
The selection of simulated alarms is done by the error simulation
counter: FRS2.ESC(2:0) which is incremented with each setting of bit
FMR0.SIM. For complete checking of the alarm indications eight
simulation steps are necessary (FRS2.ESC(2:0) = 0 after a complete
simulation).
SIM has to be held stable at high or low level for at least one receive
clock period before changing it again.
After changing RC(1:0), a receiver software reset is required
(CMDR.RRES = 1).
Force Resynchronization
Select Remote (Yellow) Alarm Format for F12 and ESF Format
(ternary or digital dual-rail interface)
F12: bit2 = 0 in every channel. ESF: pattern
“1111 1111 0000 0000” in data link channel.
F12: FS-bit of frame 12. ESF: bit2 = 0 in every channel
346
T1/J1 Registers
FALC56 V1.2
PEB 2256
2002-08-27
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