PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 84
PEB2256H-V12
Manufacturer Part Number
PEB2256H-V12
Description
IC INTERFACE LINE 3.3V 80-MQFP
Manufacturer
Infineon Technologies
Datasheet
1.PEB2256H-V12.pdf
(490 pages)
Specifications of PEB2256H-V12
Applications
*
Interface
*
Voltage - Supply
*
Package / Case
80-SQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEB2256H-V12
PEB2256H-V12IN
PEB2256H-V12IN
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Part Number
Manufacturer
Quantity
Price
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Part Number:
PEB2256H-V12
Manufacturer:
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Quantity:
10 000
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For transmit direction, contents of time slot 0 are additionally determined by the selected
transparent mode.
Table 19
enabled by
–
XSP.TT0
TSWM.TSIF
TSWM.TSIS
TSWM.TRA
TSWM.TSA(8:4)
1)
2)
3)
4)
The CRC procedure is automatically invoked when the multiframe structure is enabled.
CRC errors in the received data stream are counted by the 16-bit CRC Error Counter
CEC (one error per submultiframe, maximum).
Additionally a CRC4 error interrupt status ISR0.CRC4 is generated if enabled by
IMR0.CRC4.
All CRC bits of one outgoing submultiframe are automatically inverted in case a CRC
error is flagged for the previous received submultiframe. This function is enabled by bit
RC0.CRCI. Setting of bit RC0.XCRCI inverts the CRC bits before transmission to the
distant end. The function of RC0.XCRCI and RC0.CRCI are logically ored.
4.2.3.1
Multiframe alignment is assumed to have been lost if doubleframe alignment has been
lost (flagged on status bit FRS0.LFA). The rising edge of this bit causes an interrupt.
The multiframe resynchronization procedure starts when Doubleframe alignment has
been regained which is indicated by an interrupt status bit ISR2.FAR. For Doubleframe
synchronization refer to section Doubleframe Format. It is also be invoked by the user
by setting
• bit FMR0.FRS for complete doubleframe and multiframe resynchronization
• bit FMR1.MFCS for multiframe resynchronization only.
The CRC checking mechanism is enabled after the first correct multiframe pattern has
been found. However, CRC errors are not counted in asynchronous state.
Data Sheet
pin XDI or XSIG or XFIFO buffer (signaling controller)
Automatic transmission of the A-bit is selectable
The S
Additionally, automatic transmission of submultiframe error indication is selectable
a
-bit register XSA(8:4) can be used optionally
Synchronization Procedure
Transmit Transparent Mode (CRC Multiframe E1)
Framing +
CRC
(int. gen.)
via pin XDI
via pin XDI
via pin XDI
(int. gen.)
(int. gen.)
Transmit Transparent Source for
1)
A-Bit
XSW.XRA
via pin XDI
XSW.XRA
XSW.XRA
via pin XDI
XSW.XRA
84
2)
1)
1)
1)
S
XSW.XY0 … 4
via pin XDI
XSW.XY0 … 4
XSW.XY0 … 4
XSW.XY0 … 4
via pin XDI
a
-Bits
Functional Description E1
3)
2)
2)
2)
E-Bits
XSP.XS13/XS15
via pin XDI
(int. generated)
via pin XDI
XSP.XS13/XS15
XSP.XS13/XS15
FALC56 V1.2
PEB 2256
2002-08-27
4)
3)
3)
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