PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 296

• Manufacturer Part Number: PEB2256H-V12
• Description: IC INTERFACE LINE 3.3V 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2256H-V12

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2256H-V12; PEB2256H-V12IN

Receive Spare Bits/Additional Status (Read)
RSP
SI(2:1)
LLBDD
LLBAD
Data Sheet
SI1
7
Submultiframe Error Indication 1, 2
Not valid if doubleframe format is enabled. In this case, both bits are
set.
When using CRC-multiframe format these bits are set to
0 =
1 =
Both flags are updated with the beginning of every received CRC
multiframe.
If automatic transmission of submultiframe status is enabled by
setting bit XSP.AXS, above status information is inserted
automatically in S
(under the condition that time slot 0 transparent modes are both
disabled):
SI1
Line Loop-Back Deactivation Signal Detected
This bit is set in case of the LLB deactivate signal is detected and then
received over a period of more than 25 ms with a bit error rate less
than 10
exceed 10
If framing is aligned, the time slot 0 is not taken into account for the
error rate calculation.
Any change of this bit causes an LLBSC interrupt.
Line Loop-Back Activation Signal Detected
Depending on bit LCR1.EPRM the source of this status bit changed.
LCR1.EPRM = 0: This bit is set in case of the LLB activate signal is
detected and then received over a period of more than 25 ms with a
bit error rate less than 10
rate does not exceed 10
SI2
If multiframe alignment has been lost, or if the last multiframe
has been received with CRC error(s).
SI1 flags a CRC error in last submultiframe 1, SI2 flags a CRC
error in last submultiframe 2.
If at multiframe synchronous state last assigned submultiframe
has been received without a CRC error.
S
-2
i
. The bit remains set as long as the bit error rate does not
-bit of frame 13, SI2
-2
.
LLBDD
i
-bit position of every outgoing CRC multiframe
296
-2
-2
.
. The bit remains set as long as the bit error
LLBAD
S
i
-bit of frame 15.
RSIF
RS13
RS15
FALC56 V1.2
E1 Registers
0
PEB 2256
2002-08-27
(4F)