PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 377

• Manufacturer Part Number: PEB2256H-V12
• Description: IC INTERFACE LINE 3.3V 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2256H-V12

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2256H-V12; PEB2256H-V12IN

RESR
TTRF
DAF
Data Sheet
Rising Edge Synchronous Pulse Receive
Depending on this bit all receive system interface data and marker are
clocked with the selected active edge.
0 =
1 =
Note: If bit CMR2.IRSP is set, the behavior of signal RFM (if used) is
TTR Register Function (Fractional T1/J1 Access)
Setting this bit the function of the TTR(4:1) registers are changed. A
one in each TTR register forces the XSIGM marker high for the
corresponding time slot and controls sampling of the time slots
provided on pin XSIG. XSIG is selected by PC(4:1).XPC(3:0).
Disable Automatic Freeze
0 =
1 =
Latched with the first falling edge of the selected PCM highway
clock.
Latched with the first rising edge of the selected PCM highway
clock.
inverse (1 = falling edge, 0 = rising edge)
Signaling is automatically frozen if one of the following alarms
occurred:
Alignment (FRS0.LFA), or receive slips (ISR3.RSP/N).
Automatic freezing of signaling data is disabled. Updating of the
signaling buffer is also done if one of the above described alarm
conditions is active. However, updating of the signaling buffer
is stopped if SIC2.FFS is set. Significant only if the serial
signaling access is enabled.
Loss-Of-signal
377
(FRS0.LOS),
T1/J1 Registers
Loss-of-Frame-
FALC56 V1.2
PEB 2256
2002-08-27