PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 304

• Manufacturer Part Number: PEB2256H-V12
• Description: IC INTERFACE LINE 3.3V 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2256H-V12

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2256H-V12; PEB2256H-V12IN

Receive S
RSA4
RSA5
RSA6
RSA7
RSA8
RS4(7:0)
RS5(7:0)
RS6(7:0)
RS7(7:0)
RS8(7:0)
Data Sheet
RS47
RS57
RS67
RS77
RS87
a
4-Bit Register (Read)
7
If this bit is reset the error counter is permanently updated in the
buffer. For correct read access of the error counter bit DEC.DCEC3
has to be set. With the rising edge of this bit updating of the buffer is
stopped and the error counter is reset. Bit DEC.DCEC3 is reset
automatically with reading the error counter high byte.
If FMR1.ECM is set every second (interrupt ISR3.SEC) the error
counter is latched and then automatically reset. The latched error
counter state should be read within the next second.
Receive S
Receive S
Receive S
Receive S
Receive S
This register contains the information of the eight S
of the previously received CRC multiframe. These registers are
updated with every multiframe begin interrupt ISR0.RMB.
RS40 is received in bit-slot 4 of every service word in frame 1, RS47
in frame 15
RS50 is received in bit-slot 5, time slot 0, frame 1, RS57 in frame 15
RS60 is received in bit-slot 6, time slot 0, frame 1, RS67 in frame 15
RS70 is received in bit-slot 7, time slot 0, frame 1, RS77 in frame 15
RS80 is received in bit-slot 8, time slot 0, frame 1, RS87 in frame 15
Valid if CRC multiframe format is enabled by setting bits
FMR2.RFS1 = 1 or FMR2.RFS(1:0) = 01 (doubleframe format).
a
a
a
a
a
4-Bit Data (Y-Bits)
5-Bit Data
6-Bit Data
7-Bit Data
8-Bit Data
304
a
x bits (x = 4 to 8)
RS40
RS50
RS60
RS70
RS80
FALC56 V1.2
E1 Registers
0
PEB 2256
2002-08-27
(5C)
(5D)
(5E)
(5F)
(60)