PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 129
PEB2256H-V12
Manufacturer Part Number
PEB2256H-V12
Description
IC INTERFACE LINE 3.3V 80-MQFP
Manufacturer
Infineon Technologies
Datasheet
1.PEB2256H-V12.pdf
(490 pages)
Specifications of PEB2256H-V12
Applications
*
Interface
*
Voltage - Supply
*
Package / Case
80-SQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEB2256H-V12
PEB2256H-V12IN
PEB2256H-V12IN
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PEB2256H-V12
Manufacturer:
Infineon Technologies
Quantity:
10 000
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5.1.11
According to the input jitter defined by PUB62411 the FALC56 generates the output jitter,
which is specified in
Table 29
Specification
PUB 62411
5.1.12
The following functions are performed:
• Synchronization on pulse frame and multiframe
• Error indication when synchronization is lost. In this case, AIS is sent to the system
• Initiating and controlling of resynchronization after reaching the asynchronous state.
• Detection of remote alarm (yellow alarm) indication from the incoming data stream.
• Separation of service bits and data link bits. This information is stored in special status
• Detection of framed or unframed in-band loop-up/-down code
• Generation of various maskable interrupt statuses of the receiver functions.
• Generation of control signals to synchronize the CRC checker, and the receive elastic
If programmed and applicable to the selected multiframe format, CRC checking of the
incoming data stream is done by generating check bits for a CRC multiframe according
to the CRC6 procedure (refer to ITU-T G.704). These bits are compared with those
check bits that are received during the next CRC multiframe. If there is at least one
mismatch, the CRC error counter (16 bit) is incremented.
5.1.13
The received bit stream is stored in the receive elastic buffer. The memory is organized
as a two-frame elastic buffer with a maximum size of 2
buffer is configured independently for the receive and transmit direction. Programming
of the receive buffer size is done by SIC1.RBS1/0:
Data Sheet
side automatically and remote alarm to the remote end if enabled.
This is done automatically by the FALC56 or user controlled by the microprocessor
interface.
registers.
buffer.
Output Jitter (T1/J1)
Framer/Synchronizer (T1/J1)
Receive Elastic Buffer (T1/J1)
Output Jitter (T1/J1)
Table 29
Lower Cutoff
10 Hz
8 kHz
10 Hz
Measurement Filter Bandwidth
below.
Broadband
129
Upper Cutoff
8 kHz
40 kHz
40 kHz
Functional Description T1/J1
193 bit. The size of the elastic
Output Jitter
(UI peak to peak)
< 0.015
< 0.015
< 0.015
< 0.02
FALC56 V1.2
PEB 2256
2002-08-27
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