PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 375

• Manufacturer Part Number: PEB2256H-V12
• Description: IC INTERFACE LINE 3.3V 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2256H-V12

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2256H-V12; PEB2256H-V12IN

SSF
CRB
SSC2
SICS(2:0)
Data Sheet
Serial Signaling Format
Only applicable if pin function RSIG/XSIG and SIC3.TTRF = 0 is
selected.
0 =
1 =
Center Receive Elastic Buffer
Only
(PC(4:1).RPC(2:0) = 001
receive is generated.
A transition from low to high forces a receive slip and the read pointer
of the receive elastic buffer is centered. The delay through the buffer
is set to one half of the current buffer size. It should be hold high for
at least two 1.544 MHz periods before it is cleared.
Select System Clock
This bit together with SIC1.SSC1/0 enables the system interface to
run with a clock of 1.544, 3.088, 6.176 or 12.352 MHz (SSC2 = 1) or
2.048, 4.096, 8.192 or 16.384 MHz (SSC2 = 0).
See also register SIC1.SSC1/0 on
System Interface Channel Select
Only applicable if the system clock rate is greater than
1.544 2.048MHz.
Received data is transmitted on pin RDO/RSIG or received on
XDI XSIG with the selected system data rate. If the data rate is greater
than 1.544/2.048 Mbit/s the data is output or sampled in half, a
quarter or one eighth of the time slot. Data is not repeated. The time
while data is active during a 8
channel phase. RDO/RSIG are cleared (driven to low level) while
XDI XSIG are ignored for the remaining time of the 8
for the remaining channel phases. The channel phases are selectable
with these bits.
000 =
001 =
010 =
011 =
Bits 1 to 4 in all time slots except time slot 0 are cleared.
Bits 1 to 4 in all time slots except time slot 0 are set high.
applicable
Data active in channel phase 1, valid if system data rate is
16/8/4 or 12/6/3 Mbit/s
Data active in channel phase 2, valid if data rate is 16/8/4 or
12/6/3 Mbit/s
Data active in channel phase 3, valid if data rate is 16/8 or
12/6 Mbit/s
Data active in channel phase 4, valid if data rate is 16/8 or
12/6 Mbit/s
if
375
the
B
), no external or internal synchronous pulse
time
page
488/648 ns time slot is called a
slot
373.
assigner
T1/J1 Registers
FALC56 V1.2
488/648 ns or
is
PEB 2256
2002-08-27
disabled